/** @file
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Header file for PCH Init Common Lib
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_INIT_COMMON_LIB_H_
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#define _PCH_INIT_COMMON_LIB_H_
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#include <PchPolicyCommon.h>
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#include <PchAccess.h>
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/**
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This function returns PID according to PCIe controller index
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@param[in] ControllerIndex PCIe controller index
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@retval PCH_SBI_PID Returns PID for SBI Access
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**/
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PCH_SBI_PID
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PchGetPcieControllerSbiPid (
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IN UINT32 ControllerIndex
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);
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/**
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This function returns PID according to Root Port Number
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@param[in] RpPort Root Port Number
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@retval PCH_SBI_PID Returns PID for SBI Access
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**/
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PCH_SBI_PID
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GetRpSbiPid (
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IN UINTN RpPort
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);
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/**
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Calculate root port device number based on physical port index.
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@param[in] RpIndex Root port index (0-based).
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@retval Root port device number.
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**/
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UINT32
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PchGetPcieRpDevice (
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IN UINT32 RpIndex
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);
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/**
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This function reads Pci Config register via SBI Access
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@param[in] RpIndex Root Port Index (0-based)
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@param[in] Offset Offset of Config register
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@param[out] *Data32 Value of Config register
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@retval EFI_SUCCESS SBI Read successful.
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**/
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EFI_STATUS
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PchSbiRpPciRead32 (
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IN UINT32 RpIndex,
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IN UINT32 Offset,
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OUT UINT32 *Data32
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);
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/**
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This function And then Or Pci Config register via SBI Access
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@param[in] RpIndex Root Port Index (0-based)
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@param[in] Offset Offset of Config register
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@param[in] Data32And Value of Config register to be And-ed
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@param[in] Data32AOr Value of Config register to be Or-ed
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@retval EFI_SUCCESS SBI Read and Write successful.
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**/
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EFI_STATUS
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PchSbiRpPciAndThenOr32 (
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IN UINT32 RpIndex,
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IN UINT32 Offset,
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IN UINT32 Data32And,
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IN UINT32 Data32Or
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);
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/**
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Configure root port function number mapping
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@retval EFI_SUCCESS The function completed successfully
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**/
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EFI_STATUS
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PchConfigureRpfnMapping (
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VOID
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);
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/**
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This function lock down the P2sb SBI before going into OS.
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@param[in] SbiUnlock
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**/
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VOID
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ConfigureP2sbSbiLock (
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IN CONST BOOLEAN SbiUnlock
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);
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/**
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Bios will remove the host accessing right to Sideband register range
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prior to any 3rd party code execution.
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1) Set EPMASK5 Offset C4 (bits 29, 28, 27, 26, 17, 16, 10, 1) to disable Sideband access for PSF and MIPI controller
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2) Set EPMASK7 Offset CC (bits 6, 5) to disable Sideband access for XHCI controller
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3) Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1.
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**/
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VOID
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RemoveSidebandAccess(
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VOID
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);
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/**
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Configure PMC static function disable lock
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**/
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VOID
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ConfigurePmcStaticFunctionDisableLock (
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VOID
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);
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/**
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Print registers value
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@param[in] PrintMmioBase Mmio base address
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@param[in] PrintSize Number of registers
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@param[in] OffsetFromBase Offset from mmio base address
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@retval None
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**/
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VOID
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PrintRegisters (
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IN UINTN PrintMmioBase,
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IN UINT32 PrintSize,
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IN UINT32 OffsetFromBase
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);
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VOID
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PrintPchPciConfigSpace (
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VOID
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);
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/**
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Check if RST PCIe Storage Remapping is enabled based on policy
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@param[in] RstPcieStorageRemap The PCH PCIe Storage remapping
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@retval TRUE RST PCIe Storage Remapping is enabled
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@retval FALSE RST PCIe Storage Remapping is disabled
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**/
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BOOLEAN
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IsRstPcieStorageRemapEnabled (
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IN CONST PCH_RST_PCIE_STORAGE_CONFIG *RstPcieStorageRemap
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);
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/**
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Disable the RST remap address decoding range while RST is disabled.
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@param[in] AhciBar ABAR address
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**/
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VOID
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DisableRstRemapDecoding (
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UINT32 AhciBar
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);
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/**
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Program Xhci Port Disable Override
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@param[in] XhciMmioBase xHCI controller MBAR0 address
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@param[in] Usb2DisabledPorts Disabled USB2 ports where each port has its disabling bit
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@param[in] Usb3DisabledPorts Disabled USB3 ports where each port has its disabling bit
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@retval TRUE if platform reset is needed, otherwise FALSE is returned
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**/
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BOOLEAN
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UsbPdoProgramming (
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IN UINTN XhciMmioBase,
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IN UINT32 Usb2DisabledPorts,
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IN UINT32 Usb3DisabledPorts
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);
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#endif
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