/** @file
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Register names for PCH USB devices
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Conventions:
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- Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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- In general, PCH registers are denoted by "_PCH_" in register names
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- Registers / bits that are different between PCH generations are denoted by
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"_PCH_[generation_name]_" in register/bit names.
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- Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
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Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
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e.g., "_PCH_H_", "_PCH_LP_"
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Registers / bits names without _H_ or _LP_ apply for both H and LP.
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- Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
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at the end of the register/bit names
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- Registers / bits of new devices introduced in a PCH generation will be just named
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as "_PCH_" without [generation_name] inserted.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_USB_H_
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#define _PCH_REGS_USB_H_
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//
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// USB3 (XHCI) related definitions
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//
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#define PCI_BUS_NUMBER_PCH_XHCI 0
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#define PCI_DEVICE_NUMBER_PCH_XHCI 20
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#define PCI_FUNCTION_NUMBER_PCH_XHCI 0
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//
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// XHCI PCI Config Space registers
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//
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#define R_PCH_XHCI_MEM_BASE 0x10
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#define R_PCH_XHCI_MEM_BASE_2 0x14
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#define V_PCH_XHCI_MEM_LENGTH 0x10000
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#define N_PCH_XHCI_MEM_SHIFT 32
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#define N_PCH_XHCI_MEM_ALIGN 16
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#define B_PCH_XHCI_MEM_ALIGN_MASK 0xFFFF
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#define R_PCH_XHCI_XHCC1 0x40
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#define B_PCH_XHCI_XHCC1_ACCTRL BIT31
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#define B_PCH_XHCI_XHCC1_RMTASERR BIT24
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#define B_PCH_XHCI_XHCC1_URD BIT23
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#define B_PCH_XHCI_XHCC1_URRE BIT22
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#define B_PCH_XHCI_XHCC1_IIL1E (BIT21 | BIT20 | BIT19)
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#define V_PCH_XHCI_XHCC1_IIL1E_DIS 0
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#define V_PCH_XHCI_XHCC1_IIL1E_32 (BIT19)
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#define V_PCH_XHCI_XHCC1_IIL1E_64 (BIT20)
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#define V_PCH_XHCI_XHCC1_IIL1E_128 (BIT20 | BIT19)
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#define V_PCH_XHCI_XHCC1_IIL1E_256 (BIT21)
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#define V_PCH_XHCI_XHCC1_IIL1E_512 (BIT21 | BIT19)
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#define V_PCH_XHCI_XHCC1_IIL1E_1024 (BIT21 | BIT20)
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#define V_PCH_XHCI_XHCC1_IIL1E_131072 (BIT21 | BIT20 | BIT19)
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#define B_PCH_XHCI_XHCC1_XHCIL1E BIT18
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#define B_PCH_XHCI_XHCC1_D3IL1E BIT17
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#define B_PCH_XHCI_XHCC1_UNPPA (BIT16 | BIT15 | BIT14 | BIT13 | BIT12)
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#define B_PCH_XHCI_XHCC1_SWAXHCI BIT11
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#define B_PCH_XHCI_XHCC1_L23HRAWC (BIT10 | BIT9 | BIT8)
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#define B_PCH_XHCI_XHCC1_UTAGCP (BIT7 | BIT6)
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#define B_PCH_XHCI_XHCC1_UDAGCNP (BIT5 | BIT4)
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#define B_PCH_XHCI_XHCC1_UDAGCCP (BIT3 | BIT2)
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#define B_PCH_XHCI_XHCC1_UDAGC (BIT1 | BIT0)
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#define R_PCH_XHCI_XHCC2 0x44
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#define B_PCH_XHCI_XHCC2_OCCFDONE BIT31
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#define B_PCH_XHCI_XHCC2_XHCUPRDROE BIT11
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#define B_PCH_XHCI_XHCC2_IOSFSRAD BIT10
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#define B_PCH_XHCI_XHCC2_SWACXIHB (BIT9 | BIT8)
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#define B_PCH_XHCI_XHCC2_SWADMIL1IHB (BIT7 | BIT6)
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#define B_PCH_XHCI_XHCC2_L1FP2CGWC (BIT5 | BIT4 | BIT3)
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#define B_PCH_XHCI_XHCC2_RDREQSZCTRL (BIT2 | BIT1 | BIT0)
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#define R_PCH_XHCI_XHCLKGTEN 0x50
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#define B_PCH_XHCI_XHCLKGTEN_SSLSE BIT26
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#define B_PCH_XHCI_XHCLKGTEN_USB2PLLSE BIT25
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#define B_PCH_XHCI_XHCLKGTEN_IOSFSTCGE BIT24
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#define B_PCH_XHCI_XHCLKGTEN_HSTCGE (BIT23 | BIT22 | BIT21 | BIT20)
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#define B_PCH_XHCI_XHCLKGTEN_SSTCGE (BIT19 | BIT18 | BIT17 | BIT16)
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#define B_PCH_XHCI_XHCLKGTEN_XHCIGEU3S BIT15
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#define B_PCH_XHCI_XHCLKGTEN_XHCFTCLKSE BIT14
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#define B_PCH_XHCI_XHCLKGTEN_XHCBBTCGIPISO BIT13
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#define B_PCH_XHCI_XHCLKGTEN_XHCHSTCGU2NRWE BIT12
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#define B_PCH_XHCI_XHCLKGTEN_XHCUSB2PLLSDLE (BIT11 | BIT10)
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#define B_PCH_XHCI_XHCLKGTEN_HSPLLSUE (BIT9 | BIT8)
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#define B_PCH_XHCI_XHCLKGTEN_SSPLLSUE (BIT7 | BIT6 | BIT5)
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#define B_PCH_XHCI_XHCLKGTEN_XHCBLCGE BIT4
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#define B_PCH_XHCI_XHCLKGTEN_HSLTCGE BIT3
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#define B_PCH_XHCI_XHCLKGTEN_SSLTCGE BIT2
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#define B_PCH_XHCI_XHCLKGTEN_IOSFBTCGE BIT1
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#define B_PCH_XHCI_XHCLKGTEN_IOSFGBLCGE BIT0
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#define R_PCH_XHCI_USB_RELNUM 0x60
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#define B_PCH_XHCI_USB_RELNUM 0xFF
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#define R_PCH_XHCI_FL_ADJ 0x61
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#define B_PCH_XHCI_FL_ADJ 0x3F
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#define R_PCH_XHCI_PWR_CAPID 0x70
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#define B_PCH_XHCI_PWR_CAPID 0xFF
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#define R_PCH_XHCI_NXT_PTR1 0x71
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#define B_PCH_XHCI_NXT_PTR1 0xFF
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#define R_PCH_XHCI_PWR_CAP 0x72
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#define B_PCH_XHCI_PWR_CAP_PME_SUP 0xF800
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#define B_PCH_XHCI_PWR_CAP_D2_SUP BIT10
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#define B_PCH_XHCI_PWR_CAP_D1_SUP BIT9
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#define B_PCH_XHCI_PWR_CAP_AUX_CUR (BIT8 | BIT7 | BIT6)
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#define B_PCH_XHCI_PWR_CAP_DSI BIT5
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#define B_PCH_XHCI_PWR_CAP_PME_CLK BIT3
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#define B_PCH_XHCI_PWR_CAP_VER (BIT2 | BIT1 | BIT0)
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#define R_PCH_XHCI_PWR_CNTL_STS 0x74
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#define B_PCH_XHCI_PWR_CNTL_STS_PME_STS BIT15
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#define B_PCH_XHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13)
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#define B_PCH_XHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 | BIT9)
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#define B_PCH_XHCI_PWR_CNTL_STS_PME_EN BIT8
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#define B_PCH_XHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0)
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#define V_PCH_XHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0)
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#define R_PCH_XHCI_MSI_MCTL 0x82
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#define R_PCH_XHCI_HSCFG2 0xA4
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#define R_PCH_XHCI_SSCFG1 0xA8
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#define R_PCH_XHCI_HSCFG1 0xAC
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#define R_PCH_XHCI_U2OCM 0xB0
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#define R_PCH_XHCI_U3OCM 0xD0
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#define V_PCH_XHCI_NUMBER_OF_OC_PINS 8
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#define R_PCH_XHCI_FUS 0xE0
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#define B_PCH_XHCI_FUS_USBR (BIT5)
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#define V_PCH_XHCI_FUS_USBR_EN 0
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#define V_PCH_XHCI_FUS_USBR_DIS (BIT5)
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#define R_PCH_XHCI_FC 0xFC
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#define B_PCH_XHCI_FUS_SSPRTCNT (BIT4 | BIT3)
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#define V_PCH_XHCI_FUS_SSPRTCNT_00B 0
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#define V_PCH_XHCI_FUS_SSPRTCNT_01B (BIT3)
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#define V_PCH_XHCI_FUS_SSPRTCNT_10B (BIT4)
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#define V_PCH_XHCI_FUS_SSPRTCNT_11B (BIT4 | BIT3)
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#define B_PCH_XHCI_FUS_HSPRTCNT (BIT2 | BIT1)
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#define V_PCH_XHCI_FUS_HSPRTCNT_00B 0
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#define V_PCH_XHCI_FUS_HSPRTCNT_01B (BIT1)
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#define V_PCH_XHCI_FUS_HSPRTCNT_10B (BIT2)
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#define V_PCH_XHCI_FUS_HSPRTCNT_11B (BIT2 | BIT1)
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#define V_PCH_H_XHCI_FUS_SSPRTCNT_00B_CNT 6
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#define V_PCH_H_XHCI_FUS_SSPRTCNT_01B_CNT 4
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#define V_PCH_H_XHCI_FUS_SSPRTCNT_10B_CNT 2
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#define V_PCH_H_XHCI_FUS_SSPRTCNT_11B_CNT 0
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#define V_PCH_H_XHCI_FUS_SSPRTCNT_00B_MASK 0x3F
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#define V_PCH_H_XHCI_FUS_SSPRTCNT_01B_MASK 0x0F
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#define V_PCH_H_XHCI_FUS_SSPRTCNT_10B_MASK 0x03
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#define V_PCH_H_XHCI_FUS_SSPRTCNT_11B_MASK 0x00
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#define V_PCH_H_XHCI_FUS_HSPRTCNT_00B_CNT 14
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#define V_PCH_H_XHCI_FUS_HSPRTCNT_01B_CNT 12
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#define V_PCH_H_XHCI_FUS_HSPRTCNT_10B_CNT 10
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#define V_PCH_H_XHCI_FUS_HSPRTCNT_11B_CNT 8
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#define V_PCH_H_XHCI_FUS_HSPRTCNT_00B_MASK 0x3FFF
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#define V_PCH_H_XHCI_FUS_HSPRTCNT_01B_MASK 0x3F3F
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#define V_PCH_H_XHCI_FUS_HSPRTCNT_10B_MASK 0x03FF
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#define V_PCH_H_XHCI_FUS_HSPRTCNT_11B_MASK 0x00FF
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#define V_PCH_LP_XHCI_FIXED_SSPRTCNT 4
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#define V_PCH_LP_XHCI_FIXED_SSPRTCNT_MASK 0x0F
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#define V_PCH_LP_XHCI_FIXED_HSPRTCNT 8
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#define V_PCH_LP_XHCI_FIXED_HSPRTCNT_MASK 0x00FF
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//
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// xHCI MMIO registers
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//
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//
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// 0x00 - 0x1F - Capability Registers
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//
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#define R_PCH_XHCI_CAPLENGTH 0x00
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#define R_PCH_XHCI_HCIVERSION 0x02
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#define R_PCH_XHCI_HCSPARAMS1 0x04
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#define R_PCH_XHCI_HCSPARAMS2 0x08
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#define R_PCH_XHCI_HCSPARAMS3 0x0C
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#define B_PCH_XHCI_HCSPARAMS3_U2DEL 0xFFFF0000
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#define B_PCH_XHCI_HCSPARAMS3_U1DEL 0x0000FFFF
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#define R_PCH_XHCI_HCCPARAMS 0x10
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#define B_PCH_XHCI_HCCPARAMS_LHRC BIT5
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#define B_PCH_XHCI_HCCPARAMS_MAXPSASIZE 0xF000
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#define R_PCH_XHCI_DBOFF 0x14
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#define R_PCH_XHCI_RTSOFF 0x18
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//
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// 0x80 - 0xBF - Operational Registers
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//
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#define R_PCH_XHCI_USBCMD 0x80
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#define B_PCH_XHCI_USBCMD_RS BIT0 ///< Run/Stop
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#define B_PCH_XHCI_USBCMD_RST BIT1 ///< HCRST
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#define R_PCH_XHCI_USBSTS 0x84
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#define B_PCH_XHCI_USBSTS_HCH BIT0
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#define B_PCH_XHCI_USBSTS_CNR BIT11
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//
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// 0x480 - 0x5CF - Port Status and Control Registers
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//
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#define R_PCH_LP_XHCI_PORTSC01USB2 0x480
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#define R_PCH_LP_XHCI_PORTSC02USB2 0x490
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#define R_PCH_LP_XHCI_PORTSC03USB2 0x4A0
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#define R_PCH_LP_XHCI_PORTSC04USB2 0x4B0
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#define R_PCH_LP_XHCI_PORTSC05USB2 0x4C0
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#define R_PCH_LP_XHCI_PORTSC06USB2 0x4D0
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#define R_PCH_LP_XHCI_PORTSC07USB2 0x4E0
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#define R_PCH_LP_XHCI_PORTSC08USB2 0x4F0
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#define R_PCH_LP_XHCI_PORTSC09USB2 0x500
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#define R_PCH_LP_XHCI_PORTSC10USB2 0x510
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#define R_PCH_LP_XHCI_PORTSC11USBR 0x520
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#define R_PCH_LP_XHCI_PORTSC12USBR 0x530
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#define R_PCH_LP_XHCI_PORTSC01USB3 0x540
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#define R_PCH_LP_XHCI_PORTSC02USB3 0x550
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#define R_PCH_LP_XHCI_PORTSC03USB3 0x560
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#define R_PCH_LP_XHCI_PORTSC04USB3 0x570
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#define R_PCH_LP_XHCI_PORTSC05USB3 0x580
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#define R_PCH_LP_XHCI_PORTSC06USB3 0x590
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//
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// 0x480 - 0x5CF - Port Status and Control Registers
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//
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#define R_PCH_H_XHCI_PORTSC01USB2 0x480
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#define R_PCH_H_XHCI_PORTSC02USB2 0x490
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#define R_PCH_H_XHCI_PORTSC03USB2 0x4A0
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#define R_PCH_H_XHCI_PORTSC04USB2 0x4B0
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#define R_PCH_H_XHCI_PORTSC05USB2 0x4C0
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#define R_PCH_H_XHCI_PORTSC06USB2 0x4D0
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#define R_PCH_H_XHCI_PORTSC07USB2 0x4E0
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#define R_PCH_H_XHCI_PORTSC08USB2 0x4F0
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#define R_PCH_H_XHCI_PORTSC09USB2 0x500
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#define R_PCH_H_XHCI_PORTSC10USB2 0x510
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#define R_PCH_H_XHCI_PORTSC11USB2 0x520
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#define R_PCH_H_XHCI_PORTSC12USB2 0x530
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#define R_PCH_H_XHCI_PORTSC13USB2 0x540
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#define R_PCH_H_XHCI_PORTSC14USB2 0x550
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#define R_PCH_H_XHCI_PORTSC15USBR 0x560
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#define R_PCH_H_XHCI_PORTSC16USBR 0x570
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#define R_PCH_H_XHCI_PORTSC01USB3 0x580
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#define R_PCH_H_XHCI_PORTSC02USB3 0x590
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#define R_PCH_H_XHCI_PORTSC03USB3 0x5A0
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#define R_PCH_H_XHCI_PORTSC04USB3 0x5B0
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#define R_PCH_H_XHCI_PORTSC05USB3 0x5C0
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#define R_PCH_H_XHCI_PORTSC06USB3 0x5D0
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#define R_PCH_H_XHCI_PORTSC07USB3 0x5E0
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#define R_PCH_H_XHCI_PORTSC08USB3 0x5F0
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#define R_PCH_H_XHCI_PORTSC09USB3 0x600
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#define R_PCH_H_XHCI_PORTSC10USB3 0x610
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#define B_PCH_XHCI_PORTSCXUSB2_WPR BIT31 ///< Warm Port Reset
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#define B_PCH_XHCI_PORTSCXUSB2_CEC BIT23 ///< Port Config Error Change
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#define B_PCH_XHCI_PORTSCXUSB2_PLC BIT22 ///< Port Link State Change
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#define B_PCH_XHCI_PORTSCXUSB2_PRC BIT21 ///< Port Reset Change
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#define B_PCH_XHCI_PORTSCXUSB2_OCC BIT20 ///< Over-current Change
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#define B_PCH_XHCI_PORTSCXUSB2_WRC BIT19 ///< Warm Port Reset Change
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#define B_PCH_XHCI_PORTSCXUSB2_PEC BIT18 ///< Port Enabled Disabled Change
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#define B_PCH_XHCI_PORTSCXUSB2_CSC BIT17 ///< Connect Status Change
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#define B_PCH_XHCI_PORTSCXUSB2_LWS BIT16 ///< Port Link State Write Strobe
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#define B_PCH_XHCI_USB2_U3_EXIT (BIT5 | BIT6 | BIT7 | BIT8)
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#define B_PCH_XHCI_USB2_U0_MASK (BIT5 | BIT6 | BIT7 | BIT8)
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#define B_PCH_XHCI_PORTSCXUSB2_PP BIT9
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#define B_PCH_XHCI_PORTSCXUSB2_PLS (BIT5 | BIT6 | BIT7 | BIT8) ///< Port Link State
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#define B_PCH_XHCI_PORTSCXUSB2_PR BIT4 ///< Port Reset
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#define B_PCH_XHCI_PORTSCXUSB2_PED BIT1 ///< Port Enable/Disabled
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#define B_PCH_XHCI_PORTSCXUSB2_CCS BIT0 ///< Current Connect Status
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#define B_PCH_XHCI_PORT_CHANGE_ENABLE_MASK (B_PCH_XHCI_PORTSCXUSB2_CEC | B_PCH_XHCI_PORTSCXUSB2_PLC | B_PCH_XHCI_PORTSCXUSB2_PRC | B_PCH_XHCI_PORTSCXUSB2_OCC | B_PCH_XHCI_PORTSCXUSB2_WRC | B_PCH_XHCI_PORTSCXUSB2_PEC | B_PCH_XHCI_PORTSCXUSB2_CSC | B_PCH_XHCI_PORTSCXUSB2_PED)
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#define B_PCH_XHCI_PORTPMSCXUSB2_PTC (BIT28 | BIT29 | BIT30 | BIT31) ///< Port Test Control
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#define B_PCH_XHCI_PORTSCXUSB3_WPR BIT31 ///< Warm Port Reset
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#define B_PCH_XHCI_PORTSCXUSB3_CEC BIT23 ///< Port Config Error Change
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#define B_PCH_XHCI_PORTSCXUSB3_PLC BIT22 ///< Port Link State Change
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#define B_PCH_XHCI_PORTSCXUSB3_PRC BIT21 ///< Port Reset Change
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#define B_PCH_XHCI_PORTSCXUSB3_OCC BIT20 ///< Over-current Change
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#define B_PCH_XHCI_PORTSCXUSB3_WRC BIT19 ///< Warm Port Reset Change
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#define B_PCH_XHCI_PORTSCXUSB3_PEC BIT18 ///< Port Enabled Disabled Change
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#define B_PCH_XHCI_PORTSCXUSB3_CSC BIT17 ///< Connect Status Change
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#define B_PCH_XHCI_PORTSCXUSB3_LWS BIT16 ///< Port Link State Write Strobe
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#define B_PCH_XHCI_PORTSCXUSB3_PP BIT9 ///< Port Power
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#define B_PCH_XHCI_PORTSCXUSB3_PLS (BIT8 | BIT7 | BIT6 | BIT5) ///< Port Link State
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#define V_PCH_XHCI_PORTSCXUSB3_PLS_POLLING 0x000000E0 ///< Link is in the Polling State
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#define V_PCH_XHCI_PORTSCXUSB3_PLS_RXDETECT 0x000000A0 ///< Link is in the RxDetect State
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#define V_PCH_XHCI_PORTSCXUSB3_PLS_DISABLED 0x00000080 ///< Link is in the RxDetect State
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#define B_PCH_XHCI_PORTSCXUSB3_PR BIT4 ///< Port Reset
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#define B_PCH_XHCI_PORTSCXUSB3_PED BIT1 ///< Port Enable/Disabled
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#define B_PCH_XHCI_PORTSCXUSB3_CHANGE_ENABLE_MASK (B_PCH_XHCI_PORTSCXUSB3_CEC | B_PCH_XHCI_PORTSCXUSB3_PLC | B_PCH_XHCI_PORTSCXUSB3_PRC | B_PCH_XHCI_PORTSCXUSB3_OCC | B_PCH_XHCI_PORTSCXUSB3_WRC | B_PCH_XHCI_PORTSCXUSB3_PEC | B_PCH_XHCI_PORTSCXUSB3_CSC | B_PCH_XHCI_PORTSCXUSB3_PED)
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//
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// 0x2000 - 0x21FF - Runtime Registers
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// 0x3000 - 0x307F - Doorbell Registers
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//
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#define R_PCH_XHCI_XECP_SUPP_USB2_2 0x8008
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#define R_PCH_XHCI_XECP_SUPP_USB3_2 0x8028
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#define R_PCH_XHCI_HOST_CTRL_SCH_REG 0x8094
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#define R_PCH_XHCI_HOST_CTRL_IDMA_REG 0x809C
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#define R_PCH_XHCI_PMCTRL 0x80A4
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#define R_PCH_XHCI_PGCBCTRL 0x80A8 ///< PGCB Control
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#define R_PCH_XHCI_HOST_CTRL_MISC_REG 0x80B0 ///< Host Controller Misc Reg
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#define R_PCH_XHCI_HOST_CTRL_MISC_REG_2 0x80B4 ///< Host Controller Misc Reg 2
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#define R_PCH_XHCI_SSPE 0x80B8 ///< Super Speed Port Enables
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#define B_PCH_XHCI_LP_SSPE_MASK 0x3F ///< LP: Mask for 6 USB3 ports
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#define B_PCH_XHCI_H_SSPE_MASK 0x3FF ///< H: Mask for 10 USB3 ports
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#define R_PCH_XHCI_AUX_CTRL_REG 0x80C0 ///< AUX_CTRL_REG - AUX Reset Control
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#define R_PCH_XHCI_DUAL_ROLE_CFG0 0x80D8
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#define R_PCH_XHCI_DUAL_ROLE_CFG1 0x80DC
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#define R_PCH_XHCI_AUX_CTRL_REG1 0x80E0
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#define R_PCH_XHCI_HOST_CTRL_PORT_LINK_REG 0x80EC ///< SuperSpeed Port Link Control
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#define R_PCH_XHCI_XECP_CMDM_CTRL_REG1 0x818C ///< Command Manager Control 1
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#define R_PCH_XHCI_XECP_CMDM_CTRL_REG2 0x8190 ///< Command Manager Control 2
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#define R_PCH_XHCI_XECP_CMDM_CTRL_REG3 0x8194 ///< Command Manager Control 3
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#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW1 0x80F0 ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4
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#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW2 0x80F4 ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4
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#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW3 0x80F8 ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4
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#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW4 0x80FC ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4
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#define R_PCH_XHCI_HOST_CTRL_TRM_REG2 0x8110 ///< HOST_CTRL_TRM_REG2 - Host Controller Transfer Manager Control 2
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#define R_PCH_XHCI_AUX_CTRL_REG2 0x8154 ///< AUX_CTRL_REG2 - Aux PM Control Register 2
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#define R_PCH_XHCI_AUXCLKCTL 0x816C ///< xHCI Aux Clock Control Register
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#define R_PCH_XHCI_HOST_IF_PWR_CTRL_REG0 0x8140 ///< HOST_IF_PWR_CTRL_REG0 - Power Scheduler Control 0
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#define R_PCH_XHCI_HOST_IF_PWR_CTRL_REG1 0x8144 ///< HOST_IF_PWR_CTRL_REG1 - Power Scheduler Control 1
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#define R_PCH_XHCI_XHCLTVCTL2 0x8174 ///< xHC Latency Tolerance Parameters - LTV Control
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#define R_PCH_XHCI_LTVHIT 0x817C ///< xHC Latency Tolerance Parameters - High Idle Time Control
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#define R_PCH_XHCI_LTVMIT 0x8180 ///< xHC Latency Tolerance Parameters - Medium Idle Time Control
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#define R_PCH_XHCI_LTVLIT 0x8184 ///< xHC Latency Tolerance Parameters - Low Idle Time Control
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#define R_PCH_XHCI_USB2PHYPM 0x8164 ///< USB2 PHY Power Management Control
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#define R_PCH_XHCI_PDDIS 0x8198 ///< xHC Pulldown Disable Control
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#define R_PCH_XHCI_THROTT 0x819C ///< XHCI Throttle Control
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#define R_PCH_XHCI_LFPSPM 0x81A0 ///< LFPS PM Control
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#define R_PCH_XHCI_THROTT2 0x81B4 ///< XHCI Throttle
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#define R_PCH_XHCI_LFPSONCOUNT 0x81B8 ///< LFPS On Count
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#define R_PCH_XHCI_D0I2CTRL 0x81BC ///< D0I2 Control Register
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#define R_PCH_XHCI_USB2PMCTRL 0x81C4 ///< USB2 Power Management Control
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//
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// SKL PCH LP FUSE
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//
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#define R_PCH_XHCI_LP_FUSE1 0x8410
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#define B_PCH_XHCI_LP_FUS_HSPRTCNT (BIT1)
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#define B_PCH_XHCI_LP_FUS_USBR (BIT5)
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#define R_PCH_XHCI_STRAP2 0x8420 ///< USB3 Mode Strap
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#define B_PCH_XHCI_STRAP2_USB3_SSIC_MODE (BIT1 | BIT0) ///< USB3/SSIC Mode
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#define R_PCH_XHCI_USBLEGCTLSTS 0x8470 ///< USB Legacy Support Control Status
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#define B_PCH_XHCI_USBLEGCTLSTS_SMIBAR BIT31 ///< SMI on BAR Status
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#define B_PCH_XHCI_USBLEGCTLSTS_SMIPCIC BIT30 ///< SMI on PCI Command Status
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#define B_PCH_XHCI_USBLEGCTLSTS_SMIOSC BIT29 ///< SMI on OS Ownership Change Status
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#define B_PCH_XHCI_USBLEGCTLSTS_SMIBARE BIT15 ///< SMI on BAR Enable
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#define B_PCH_XHCI_USBLEGCTLSTS_SMIPCICE BIT14 ///< SMI on PCI Command Enable
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#define B_PCH_XHCI_USBLEGCTLSTS_SMIOSOE BIT13 ///< SMI on OS Ownership Enable
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#define B_PCH_XHCI_USBLEGCTLSTS_SMIHSEE BIT4 ///< SMI on Host System Error Enable
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#define B_PCH_XHCI_USBLEGCTLSTS_USBSMIE BIT0 ///< USB SMI Enable
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//
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// Extended Capability Registers
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//
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#define R_PCH_XHCI_USB2PDO 0x84F8
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#define B_PCH_XHCI_LP_USB2PDO_MASK 0x3FF ///< LP: Mask for 10 USB2 ports
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#define B_PCH_XHCI_H_USB2PDO_MASK 0x7FFF ///< H: Mask for 14 USB2 ports
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#define B_PCH_XHCI_USB2PDO_DIS_PORT0 BIT0
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#define R_PCH_XHCI_USB3PDO 0x84FC
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#define B_PCH_XHCI_LP_USB3PDO_MASK 0x3F ///< LP: Mask for 6 USB3 ports
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#define B_PCH_XHCI_H_USB3PDO_MASK 0x3FF ///< H: Mask for 10 USB3 ports
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#define B_PCH_XHCI_USB3PDO_DIS_PORT0 BIT0
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//
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// Debug Capability Descriptor Parameters
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//
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#define R_PCH_XHCI_DBC_DBCCTL 0x8760 ///< DBCCTL - DbC Control
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//
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// xDCI (OTG) USB Device Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_XDCI 20
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#define PCI_FUNCTION_NUMBER_PCH_XDCI 1
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//
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// xDCI (OTG) PCI Config Space Registers
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//
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#define R_PCH_XDCI_MEM_BASE 0x10
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#define V_PCH_XDCI_MEM_LENGTH 0x200000
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#define R_PCH_XDCI_PMCSR 0x84 ///< Power Management Control and Status Register
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#define R_PCH_XDCI_GENERAL_PURPOSER_REG1 0xA0 ///< General Purpose PCI RW Register1
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#define R_PCH_XDCI_CPGE 0xA2 ///< Chassis Power Gate Enable
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#define R_PCH_XDCI_GENERAL_PURPOSER_REG4 0xAC ///< General Purpose PCI RW Register4
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#define R_PCH_OTG_GENERAL_INPUT_REG 0xC0 ///< General Input Register
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//
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// xDCI (OTG) MMIO registers
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//
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#define R_PCH_XDCI_GCTL 0xC110 ///< Xdci Global Ctrl
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#define B_PCH_XDCI_GCTL_GHIBEREN BIT1 ///< Hibernation enable
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#define R_PCH_XDCI_GUSB2PHYCFG 0xC200 ///< Global USB2 PHY Configuration Register
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#define B_PCH_XDCI_GUSB2PHYCFG_SUSPHY BIT6 ///< Suspend USB2.0 HS/FS/LS PHY
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#define R_PCH_XDCI_GUSB3PIPECTL0 0xC2C0 ///< Global USB3 PIPE Control Register 0
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#define B_PCH_XDCI_GUSB3PIPECTL0_UX_IN_PX BIT27 ///< Ux Exit in Px
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#define R_PCH_XDCI_APBFC_U3PMU_CFG2 0x10F810
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#define R_PCH_XDCI_APBFC_U3PMU_CFG4 0x10F818
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#define R_PCH_XDCI_APBFC_U3PMU_CFG5 0x10F81C
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#define R_PCH_XDCI_APBFC_U3PMU_CFG6 0x10F820
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//
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// xDCI (OTG) Private Configuration Registers
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// (PID:OTG)
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//
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#define R_PCH_PCR_OTG_IOSF_A2 0xA2
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#define R_PCH_PCR_OTG_IOSF_PMCTL 0x1D0
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#define R_PCH_PCR_OTG_PCICFGCTRL1 0x200
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#define B_PCH_PCR_OTG_PCICFGCTRL_PCI_IRQ 0x0FF00000
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#define N_PCH_PCR_OTG_PCICFGCTRL_PCI_IRQ 20
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#define B_PCH_PCR_OTG_PCICFGCTRL_ACPI_IRQ 0x000FF000
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#define N_PCH_PCR_OTG_PCICFGCTRL_ACPI_IRQ 12
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#define B_PCH_PCR_OTG_PCICFGCTRL_INT_PIN 0x00000F00
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#define N_PCH_PCR_OTG_PCICFGCTRL_INT_PIN 8
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#define B_PCH_PCR_OTG_PCICFGCTRL_BAR1_DIS 0x00000080
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#define B_PCH_PCR_OTG_PCICFGCTRL_PME_SUP 0x0000007C
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#define B_PCH_PCR_OTG_PCICFGCTRL_ACPI_INT_EN 0x00000002
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#define B_PCH_PCR_OTG_PCICFGCTRL_PCI_CFG_DIS 0x00000001
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//
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// USB2 Private Configuration Registers
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// USB2 HIP design featured
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// (PID:USB2)
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//
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#define R_PCH_PCR_USB2_GLOBAL_PORT 0x4001 ///< USB2 GLOBAL PORT
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#define R_PCH_PCR_USB2_400C 0x400C
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#define R_PCH_PCR_USB2_PP_LANE_BASE_ADDR 0x4000 ///< PP LANE base address
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#define V_PCH_PCR_USB2_PER_PORT 0x00 ///< USB2 PER PORT Addr[7:2] = 0x00
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#define V_PCH_PCR_USB2_UTMI_MISC_PER_PORT 0x08 ///< UTMI MISC REG PER PORT Addr[7:2] = 0x08
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#define V_PCH_PCR_USB2_PER_PORT_2 0x26 ///< USB2 PER PORT 2 Addr[7:2] = 0x26
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#define R_PCH_PCR_USB2_402A 0x402A
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#define R_PCH_PCR_USB2_GLB_ADP_VBUS_REG 0x402B ///< GLB ADP VBUS REG
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#define R_PCH_PCR_USB2_GLOBAL_PORT_2 0x402C ///< USB2 GLOBAL PORT 2
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#define R_PCH_PCR_USB2_7034 0x7034
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#define R_PCH_PCR_USB2_7038 0x7038
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#define R_PCH_PCR_USB2_703C 0x703C
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#define R_PCH_PCR_USB2_7040 0x7040
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#define R_PCH_PCR_USB2_7044 0x7044
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#define R_PCH_PCR_USB2_7048 0x7048
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#define R_PCH_PCR_USB2_704C 0x704C
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#define R_PCH_PCR_USB2_CFG_COMPBG 0x7F04 ///< USB2 COMPBG
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//
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// xHCI SSIC registers
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//
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#define R_PCH_XHCI_SSIC_GLOBAL_CONF_CTRL 0x8804 ///< SSIC Global Configuration Control
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#define R_PCH_XHCI_SSIC_CONF_REG1_PORT_1 0x8808 ///< SSIC Configuration Register 1 Port 1
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#define R_PCH_XHCI_SSIC_CONF_REG2_PORT_1 0x880C ///< SSIC Configuration Register 2 Port 1
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#define R_PCH_XHCI_SSIC_CONF_REG3_PORT_1 0x8810 ///< SSIC Configuration Register 3 Port 1
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#define R_PCH_XHCI_SSIC_CONF_REG1_PORT_2 0x8838 ///< SSIC Configuration Register 1 Port 2
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#define R_PCH_XHCI_SSIC_CONF_REG2_PORT_2 0x883C ///< SSIC Configuration Register 2 Port 2
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#define R_PCH_XHCI_SSIC_CONF_REG3_PORT_2 0x8840 ///< SSIC Configuration Register 3 Port 2
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#define B_PCH_XHCI_SSIC_CONF_REG2_PORT_UNUSED BIT31
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#define B_PCH_XHCI_SSIC_CONF_REG2_PROG_DONE BIT30
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#define R_PCH_XHCI_SSIC_PROF_ATTR_PORT_1 0x8900 ///< Profile Attributes: Port 1 ... N
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#define R_PCH_XHCI_SSIC_ACCESS_CONT_PORT_1 0x8904 ///< SSIC Port N Register Access Control: Port 1
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#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_0C 0x890C
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#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_10 0x8910
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#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_14 0x8914
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#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_18 0x8918
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#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_1C 0x891C
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#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_20 0x8920
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#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_24 0x8924
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#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_28 0x8928
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#define R_PCH_XHCI_SSIC_PROF_ATTR_PORT_2 0x8A10 ///< Profile Attributes: Port 2 ... N
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#define R_PCH_XHCI_SSIC_ACCESS_CONT_PORT_2 0x8A14 ///< SSIC Port N Register Access Control: Port 2
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#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_0C 0x8A1C
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#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_10 0x8A20
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#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_14 0x8A24
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#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_18 0x8A28
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#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_1C 0x8A2C
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#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_20 0x8A30
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#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_24 0x8A34
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#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_28 0x8A38
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#endif
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