/** @file
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Register names for PCH TraceHub device
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Conventions:
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- Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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- In general, PCH registers are denoted by "_PCH_" in register names
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- Registers / bits that are different between PCH generations are denoted by
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"_PCH_[generation_name]_" in register/bit names.
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- Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
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Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
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e.g., "_PCH_H_", "_PCH_LP_"
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Registers / bits names without _H_ or _LP_ apply for both H and LP.
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- Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
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at the end of the register/bit names
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- Registers / bits of new devices introduced in a PCH generation will be just named
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as "_PCH_" without [generation_name] inserted.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_TRACE_HUB_H_
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#define _PCH_REGS_TRACE_HUB_H_
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//
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// TraceHub Registers (D31:F7)
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//
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#define PCI_DEVICE_NUMBER_PCH_TRACE_HUB 31
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#define PCI_FUNCTION_NUMBER_PCH_TRACE_HUB 7
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#define R_PCH_TRACE_HUB_CSR_MTB_LBAR 0x10
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#define B_PCH_TRACE_HUB_CSR_MTB_RBAL 0xFFF00000
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#define R_PCH_TRACE_HUB_CSR_MTB_UBAR 0x14
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#define B_PCH_TRACE_HUB_CSR_MTB_RBAU 0xFFFFFFFF
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#define R_PCH_TRACE_HUB_SW_LBAR 0x18
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#define B_PCH_TRACE_HUB_SW_RBAL 0xFFE00000
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#define R_PCH_TRACE_HUB_SW_UBAR 0x1C
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#define B_PCH_TRACE_HUB_SW_RBAU 0xFFFFFFFF
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#define R_PCH_TRACE_HUB_RTIT_LBAR 0x20
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#define B_PCH_TRACE_HUB_RTIT_RBAL 0xFFFFFF00
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#define R_PCH_TRACE_HUB_RTIT_UBAR 0x24
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#define B_PCH_TRACE_HUB_RTIT_RBAU 0xFFFFFFFF
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#define R_PCH_TRACE_HUB_MSICID 0x40
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#define R_PCH_TRACE_HUB_MSINCP 0x41
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#define R_PCH_TRACE_HUB_MSIMC 0x42
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#define R_PCH_TRACE_HUB_MSILMA 0x44
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#define R_PCH_TRACE_HUB_MSIUMA 0x48
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#define R_PCH_TRACE_HUB_MSIMD 0x4C
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#define B_PCH_TRACE_HUB_FW_RBAL 0xFFFC0000
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#define B_PCH_TRACE_HUB_FW_RBAU 0xFFFFFFFF
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#define R_PCH_TRACE_HUB_DSC 0x80
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#define B_PCH_TRACE_HUB_BYP BIT0 //< TraceHub Bypass
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#define R_PCH_TRACE_HUB_DSS 0x81
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#define R_PCH_TRACE_HUB_ISTOT 0x84
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#define R_PCH_TRACE_HUB_ICTOT 0x88
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#define R_PCH_TRACE_HUB_IPAD 0x8C
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#define R_PCH_TRACE_HUB_DSD 0x90
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//
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// Offsets from CSR_MTB_BAR
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//
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#define R_PCH_TRACE_HUB_MTB_GTHOPT0 0x00
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#define B_PCH_TRACE_HUB_MTB_GTHOPT0_P0FLUSH BIT7
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#define B_PCH_TRACE_HUB_MTB_GTHOPT0_P1FLUSH BIT15
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#define V_PCH_TRACE_HUB_MTB_SWDEST_PTI 0x0A
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#define V_PCH_TRACE_HUB_MTB_SWDEST_MEMEXI 0x08
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#define V_PCH_TRACE_HUB_MTB_SWDEST_DISABLE 0x00
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#define R_PCH_TRACE_HUB_MTB_SWDEST_1 0x0C
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#define B_PCH_TRACE_HUB_MTB_SWDEST_CSE_1 0x0000000F
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#define B_PCH_TRACE_HUB_MTB_SWDEST_CSE_2 0x000000F0
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#define B_PCH_TRACE_HUB_MTB_SWDEST_CSE_3 0x00000F00
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#define B_PCH_TRACE_HUB_MTB_SWDEST_ISH_1 0x0000F000
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#define B_PCH_TRACE_HUB_MTB_SWDEST_ISH_2 0x000F0000
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#define B_PCH_TRACE_HUB_MTB_SWDEST_ISH_3 0x00F00000
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#define B_PCH_TRACE_HUB_MTB_SWDEST_AUDIO 0x0F000000
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#define B_PCH_TRACE_HUB_MTB_SWDEST_PMC 0xF0000000
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#define R_PCH_TRACE_HUB_MTB_SWDEST_2 0x10
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#define B_PCH_TRACE_HUB_MTB_SWDEST_FTH 0x0000000F
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#define R_PCH_TRACE_HUB_MTB_SWDEST_3 0x14
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#define B_PCH_TRACE_HUB_MTB_SWDEST_MAESTRO 0x00000F00
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#define B_PCH_TRACE_HUB_MTB_SWDEST_SKYCAM 0x0F000000
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#define B_PCH_TRACE_HUB_MTB_SWDEST_AET 0xF0000000
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#define R_PCH_TRACE_HUB_MTB_SWDEST_4 0x18
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#define R_PCH_TRACE_HUB_MTB_MSC0CTL 0xA0100
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#define R_PCH_TRACE_HUB_MTB_MSC1CTL 0xA0200
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#define V_PCH_TRACE_HUB_MTB_MSCNMODE_DCI 0x2
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#define V_PCH_TRACE_HUB_MTB_MSCNMODE_DEBUG 0x3
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#define B_PCH_TRACE_HUB_MTB_MSCNLEN (BIT10 | BIT9 | BIT8)
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#define B_PCH_TRACE_HUB_MTB_MSCNMODE (BIT5 | BIT4)
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#define N_PCH_TRACE_HUB_MTB_MSCNMODE 0x4
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#define B_PCH_TRACE_HUB_MTB_MSCN_RD_HDR_OVRD BIT2
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#define B_PCH_TRACE_HUB_MTB_WRAPENN BIT1
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#define B_PCH_TRACE_HUB_MTB_MSCNEN BIT0
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#define R_PCH_TRACE_HUB_MTB_GTHSTAT 0xD4
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#define R_PCH_TRACE_HUB_MTB_SCR2 0xD8
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#define B_PCH_TRACE_HUB_MTB_SCR2_FCD BIT0
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#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF2 BIT2
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#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF3 BIT3
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#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF4 BIT4
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#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF5 BIT5
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#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF6 BIT6
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#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF7 BIT7
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#define R_PCH_TRACE_HUB_MTB_MSC0BAR 0xA0108
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#define R_PCH_TRACE_HUB_MTB_MSC0SIZE 0xA010C
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#define R_PCH_TRACE_HUB_MTB_MSC1BAR 0xA0208
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#define R_PCH_TRACE_HUB_MTB_MSC1SIZE 0xA020C
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#define R_PCH_TRACE_HUB_MTB_STREAMCFG1 0xA1000
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#define B_PCH_TRACE_HUB_MTB_STREAMCFG1_ENABLE BIT28
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#define R_PCH_TRACE_HUB_MTB_PTI_CTL 0x1C00
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#define B_PCH_TRACE_HUB_MTB_PTIMODESEL 0xF0
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#define B_PCH_TRACE_HUB_MTB_PTICLKDIV (BIT17 | BIT16)
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#define B_PCH_TRACE_HUB_MTB_PATGENMOD (BIT22 | BIT21 | BIT20)
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#define B_PCH_TRACE_HUB_MTB_PTI_EN BIT0
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#define R_PCH_TRACE_HUB_MTB_SCR 0xC8
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#define R_PCH_TRACE_HUB_MTB_GTH_FREQ 0xCC
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#define V_PCH_TRACE_HUB_MTB_SCR 0x00130000
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#define R_PCH_TRACE_HUB_CSR_MTB_SCRATCHPAD0 0xE0
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#define R_PCH_TRACE_HUB_CSR_MTB_SCRATCHPAD1 0xE4
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#define R_PCH_TRACE_HUB_CSR_MTB_SCRATCHPAD10 0xE40
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#define R_PCH_TRACE_HUB_MTB_CTPGCS 0x1C14
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#define B_PCH_TRACE_HUB_MTB_CTPEN BIT0
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#define V_PCH_TRACE_HUB_MTB_CHLCNT 0x80
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#define V_PCH_TRACE_HUB_MTB_STHMSTR 0x20
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#define R_PCH_TRACE_HUB_CSR_MTB_TSUCTRL 0x2000
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#define B_PCH_TRACE_HUB_CSR_MTB_TSUCTRL_CTCRESYNC BIT0
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#endif
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