/** @file
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Register names for PCH Thermal Device
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Conventions:
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- Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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- In general, PCH registers are denoted by "_PCH_" in register names
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- Registers / bits that are different between PCH generations are denoted by
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"_PCH_[generation_name]_" in register/bit names.
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- Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
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Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
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e.g., "_PCH_H_", "_PCH_LP_"
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Registers / bits names without _H_ or _LP_ apply for both H and LP.
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- Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
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at the end of the register/bit names
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- Registers / bits of new devices introduced in a PCH generation will be just named
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as "_PCH_" without [generation_name] inserted.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_THERMAL_H_
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#define _PCH_REGS_THERMAL_H_
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//
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// Thermal Device Registers (D20:2)
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//
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#define PCI_DEVICE_NUMBER_PCH_THERMAL 20
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#define PCI_FUNCTION_NUMBER_PCH_THERMAL 2
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#define R_PCH_THERMAL_TBAR 0x10
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#define V_PCH_THERMAL_TBAR_SIZE (4 * 1024)
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#define N_PCH_THREMAL_TBAR_ALIGNMENT 12
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#define B_PCH_THERMAL_TBAR_MASK 0xFFFFF000
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#define R_PCH_THERMAL_TBARH 0x14
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#define R_PCH_THERMAL_TBARB 0x40
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#define V_PCH_THERMAL_TBARB_SIZE (4 * 1024)
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#define N_PCH_THREMAL_TBARB_ALIGNMENT 12
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#define B_PCH_THERMAL_SPTYPEN BIT0
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#define R_PCH_THERMAL_TBARBH 0x44
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#define B_PCH_THERMAL_TBARB_MASK 0xFFFFF000
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//
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// Thermal TBAR MMIO registers
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//
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#define R_PCH_TBAR_TSC 0x04
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#define B_PCH_TBAR_TSC_PLD BIT7
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#define B_PCH_TBAR_TSC_CPDE BIT0
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#define R_PCH_TBAR_TSS 0x06
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#define R_PCH_TBAR_TSEL 0x08
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#define B_PCH_TBAR_TSEL_PLD BIT7
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#define B_PCH_TBAR_TSEL_ETS BIT0
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#define R_PCH_TBAR_TSREL 0x0A
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#define R_PCH_TBAR_TSMIC 0x0C
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#define B_PCH_TBAR_TSMIC_PLD BIT7
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#define B_PCH_TBAR_TSMIC_SMIE BIT0
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#define R_PCH_TBAR_CTT 0x10
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#define R_PCH_TBAR_TAHV 0x14
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#define R_PCH_TBAR_TALV 0x18
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#define R_PCH_TBAR_TSPM 0x1C
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#define B_PCH_TBAR_TSPM_LTT (BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
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#define V_PCH_TBAR_TSPM_LTT 0x0C8
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#define B_PCH_TBAR_TSPM_MAXTSST (BIT11 | BIT10 | BIT9)
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#define V_PCH_TBAR_TSPM_MAXTSST (0x4 << 9)
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#define B_PCH_TBAR_TSPM_MINTSST BIT12
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#define B_PCH_TBAR_TSPM_DTSSIC0 BIT13
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#define B_PCH_TBAR_TSPM_DTSSS0EN BIT14
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#define B_PCH_TBAR_TSPM_TSPMLOCK BIT15
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#define R_PCH_TBAR_TL 0x40
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#define B_PCH_TBAR_TL_LOCK BIT31
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#define B_PCH_TBAR_TL_TTEN BIT29
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#define R_PCH_TBAR_TL2 0x50
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#define R_PCH_TBAR_TL2_LOCK BIT15
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#define R_PCH_TBAR_TL2_PMCTEN BIT14
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#define R_PCH_TBAR_PHL 0x60
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#define B_PCH_TBAR_PHLE BIT15
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#define R_PCH_TBAR_PHLC 0x62
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#define B_PCH_TBAR_PHLC_LOCK BIT0
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#define R_PCH_TBAR_TAS 0x80
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#define R_PCH_TBAR_TSPIEN 0x82
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#define R_PCH_TBAR_TSGPEN 0x84
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#define B_PCH_TBAR_TL2_PMCTEN BIT14
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#define R_PCH_TBAR_A4 0xA4
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#define R_PCH_TBAR_C0 0xC0
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#define R_PCH_TBAR_C4 0xC4
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#define R_PCH_TBAR_C8 0xC8
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#define R_PCH_TBAR_CC 0xCC
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#define R_PCH_TBAR_D0 0xD0
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#define R_PCH_TBAR_E0 0xE0
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#define R_PCH_TBAR_E4 0xE4
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#define R_PCH_TBAR_E8 0xE8
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#define R_PCH_TBAR_TCFD 0xF0 ///< Thermal controller function disable
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#define B_PCH_TBAR_TCFD_TCD BIT0 ///< Thermal controller disable
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#endif
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