/** @file
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Register names for PCH Smbus Device.
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Conventions:
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- Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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- In general, PCH registers are denoted by "_PCH_" in register names
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- Registers / bits that are different between PCH generations are denoted by
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"_PCH_[generation_name]_" in register/bit names.
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- Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
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Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
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e.g., "_PCH_H_", "_PCH_LP_"
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Registers / bits names without _H_ or _LP_ apply for both H and LP.
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- Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
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at the end of the register/bit names
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- Registers / bits of new devices introduced in a PCH generation will be just named
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as "_PCH_" without [generation_name] inserted.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_SMBUS_H_
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#define _PCH_REGS_SMBUS_H_
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//
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// SMBus Controller Registers (D31:F4)
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//
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#define PCI_DEVICE_NUMBER_PCH_SMBUS 31
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#define PCI_FUNCTION_NUMBER_PCH_SMBUS 4
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#define R_PCH_SMBUS_BASE 0x20
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#define V_PCH_SMBUS_BASE_SIZE (1 << 5)
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#define B_PCH_SMBUS_BASE_BAR 0x0000FFE0
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#define R_PCH_SMBUS_HOSTC 0x40
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#define B_PCH_SMBUS_HOSTC_SPDWD BIT4
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#define B_PCH_SMBUS_HOSTC_SSRESET BIT3
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#define B_PCH_SMBUS_HOSTC_I2C_EN BIT2
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#define B_PCH_SMBUS_HOSTC_SMI_EN BIT1
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#define B_PCH_SMBUS_HOSTC_HST_EN BIT0
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#define R_PCH_SMBUS_TCOBASE 0x50
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#define B_PCH_SMBUS_TCOBASE_BAR 0x0000FFE0
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#define R_PCH_SMBUS_TCOCTL 0x54
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#define B_PCH_SMBUS_TCOCTL_TCO_BASE_EN BIT8
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#define B_PCH_SMBUS_TCOCTL_TCO_BASE_LOCK BIT0
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#define R_PCH_SMBUS_64 0x64
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#define R_PCH_SMBUS_80 0x80
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//
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// SMBus I/O Registers
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//
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#define R_PCH_SMBUS_HSTS 0x00 ///< Host Status Register R/W
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#define B_PCH_SMBUS_HBSY 0x01
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#define B_PCH_SMBUS_INTR 0x02
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#define B_PCH_SMBUS_DERR 0x04
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#define B_PCH_SMBUS_BERR 0x08
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#define B_PCH_SMBUS_FAIL 0x10
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#define B_PCH_SMBUS_SMBALERT_STS 0x20
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#define B_PCH_SMBUS_IUS 0x40
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#define B_PCH_SMBUS_BYTE_DONE_STS 0x80
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#define B_PCH_SMBUS_ERROR (B_PCH_SMBUS_DERR | B_PCH_SMBUS_BERR | B_PCH_SMBUS_FAIL)
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#define B_PCH_SMBUS_HSTS_ALL 0xFF
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#define R_PCH_SMBUS_HCTL 0x02 ///< Host Control Register R/W
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#define B_PCH_SMBUS_INTREN 0x01
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#define B_PCH_SMBUS_KILL 0x02
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#define B_PCH_SMBUS_SMB_CMD 0x1C
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#define V_PCH_SMBUS_SMB_CMD_QUICK 0x00
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#define V_PCH_SMBUS_SMB_CMD_BYTE 0x04
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#define V_PCH_SMBUS_SMB_CMD_BYTE_DATA 0x08
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#define V_PCH_SMBUS_SMB_CMD_WORD_DATA 0x0C
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#define V_PCH_SMBUS_SMB_CMD_PROCESS_CALL 0x10
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#define V_PCH_SMBUS_SMB_CMD_BLOCK 0x14
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#define V_PCH_SMBUS_SMB_CMD_IIC_READ 0x18
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#define V_PCH_SMBUS_SMB_CMD_BLOCK_PROCESS 0x1C
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#define B_PCH_SMBUS_LAST_BYTE 0x20
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#define B_PCH_SMBUS_START 0x40
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#define B_PCH_SMBUS_PEC_EN 0x80
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#define R_PCH_SMBUS_HCMD 0x03 ///< Host Command Register R/W
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#define R_PCH_SMBUS_TSA 0x04 ///< Transmit Slave Address Register R/W
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#define B_PCH_SMBUS_RW_SEL 0x01
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#define B_PCH_SMBUS_READ 0x01 // RW
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#define B_PCH_SMBUS_WRITE 0x00 // RW
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#define B_PCH_SMBUS_ADDRESS 0xFE
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#define R_PCH_SMBUS_HD0 0x05 ///< Data 0 Register R/W
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#define R_PCH_SMBUS_HD1 0x06 ///< Data 1 Register R/W
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#define R_PCH_SMBUS_HBD 0x07 ///< Host Block Data Register R/W
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#define R_PCH_SMBUS_PEC 0x08 ///< Packet Error Check Data Register R/W
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#define R_PCH_SMBUS_RSA 0x09 ///< Receive Slave Address Register R/W
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#define B_PCH_SMBUS_SLAVE_ADDR 0x7F
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#define R_PCH_SMBUS_SD 0x0A ///< Receive Slave Data Register R/W
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#define R_PCH_SMBUS_AUXS 0x0C ///< Auxiliary Status Register R/WC
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#define B_PCH_SMBUS_CRCE 0x01
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#define B_PCH_SMBUS_STCO 0x02 ///< SMBus TCO Mode
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#define R_PCH_SMBUS_AUXC 0x0D ///< Auxiliary Control Register R/W
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#define B_PCH_SMBUS_AAC 0x01
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#define B_PCH_SMBUS_E32B 0x02
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#define R_PCH_SMBUS_SMLC 0x0E ///< SMLINK Pin Control Register R/W
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#define B_PCH_SMBUS_SMLINK0_CUR_STS 0x01
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#define B_PCH_SMBUS_SMLINK1_CUR_STS 0x02
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#define B_PCH_SMBUS_SMLINK_CLK_CTL 0x04
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#define R_PCH_SMBUS_SMBC 0x0F ///< SMBus Pin Control Register R/W
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#define B_PCH_SMBUS_SMBCLK_CUR_STS 0x01
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#define B_PCH_SMBUS_SMBDATA_CUR_STS 0x02
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#define B_PCH_SMBUS_SMBCLK_CTL 0x04
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#define R_PCH_SMBUS_SSTS 0x10 ///< Slave Status Register R/WC
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#define B_PCH_SMBUS_HOST_NOTIFY_STS 0x01
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#define R_PCH_SMBUS_SCMD 0x11 ///< Slave Command Register R/W
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#define B_PCH_SMBUS_HOST_NOTIFY_INTREN 0x01
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#define B_PCH_SMBUS_HOST_NOTIFY_WKEN 0x02
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#define B_PCH_SMBUS_SMBALERT_DIS 0x04
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#define R_PCH_SMBUS_NDA 0x14 ///< Notify Device Address Register RO
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#define B_PCH_SMBUS_DEVICE_ADDRESS 0xFE
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#define R_PCH_SMBUS_NDLB 0x16 ///< Notify Data Low Byte Register RO
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#define R_PCH_SMBUS_NDHB 0x17 ///< Notify Data High Byte Register RO
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//
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// SMBus Private Config Registers
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// (PID:SMB)
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//
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#define R_PCH_PCR_SMBUS_TCOCFG 0x00 ///< TCO Configuration register
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#define B_PCH_PCR_SMBUS_TCOCFG_IE BIT7 ///< TCO IRQ Enable
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#define B_PCH_PCR_SMBUS_TCOCFG_IS (BIT2 | BIT1 | BIT0) ///< TCO IRQ Select
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#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_9 0x00
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#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_10 0x01
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#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_11 0x02
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#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_20 0x04 ///< only if APIC enabled
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#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_21 0x05 ///< only if APIC enabled
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#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_22 0x06 ///< only if APIC enabled
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#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_23 0x07 ///< only if APIC enabled
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#define R_PCH_PCR_SMBUS_SMBTM 0x04 ///< SMBus Test Mode
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#define B_PCH_PCR_SMBUS_SMBTM_SMBCT BIT1 ///< SMBus Counter
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#define B_PCH_PCR_SMBUS_SMBTM_SMBDG BIT0 ///< SMBus Deglitch
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#define R_PCH_PCR_SMBUS_SCTM 0x08 ///< Short Counter Test Mode
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#define B_PCH_PCR_SMBUS_SCTM_SSU BIT31 ///< Simulation Speed-Up
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#define R_PCH_PCR_SMBUS_GC 0x0C ///< General Control
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#define B_PCH_PCR_SMBUS_GC_FD BIT0 ///< Function Disable
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#define B_PCH_PCR_SMBUS_GC_NR BIT1 ///< No Reboot
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#define B_PCH_PCR_SMBUS_GC_SMBSCGE BIT2 ///< SMB Static Clock Gating Enable
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#endif
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