/** @file
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Register names for PCH Storage and Communication Subsystem
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Conventions:
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- Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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- In general, PCH registers are denoted by "_PCH_" in register names
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- Registers / bits that are different between PCH generations are denoted by
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"_PCH_[generation_name]_" in register/bit names.
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- Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
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Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
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e.g., "_PCH_H_", "_PCH_LP_"
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Registers / bits names without _H_ or _LP_ apply for both H and LP.
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- Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
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at the end of the register/bit names
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- Registers / bits of new devices introduced in a PCH generation will be just named
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as "_PCH_" without [generation_name] inserted.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_SCS_H_
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#define _PCH_REGS_SCS_H_
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//
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// SCS eMMC Controller Registers (D30:F4)
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//
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#define PCI_DEVICE_NUMBER_PCH_SCS_EMMC 30
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#define PCI_FUNCTION_NUMBER_PCH_SCS_EMMC 4
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#define V_PCH_SCS_EMMC_VENDOR_ID V_PCH_INTEL_VENDOR_ID
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#define V_PCH_SCS_EMMC_DEVICE_ID 0x9D2B
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//
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// SCS SDIO Controller Registers (D30:F5)
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//
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#define PCI_DEVICE_NUMBER_PCH_SCS_SDIO 30
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#define PCI_FUNCTION_NUMBER_PCH_SCS_SDIO 5
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#define V_PCH_SCS_SDIO_VENDOR_ID V_PCH_INTEL_VENDOR_ID
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#define V_PCH_SCS_SDIO_DEVICE_ID 0x9D2C
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//
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// SCS SDCARD Controller Registers (D30:F6)
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//
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#define PCI_DEVICE_NUMBER_PCH_SCS_SDCARD 30
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#define PCI_FUNCTION_NUMBER_PCH_SCS_SDCARD 6
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#define V_PCH_SCS_SDCARD_VENDOR_ID V_PCH_INTEL_VENDOR_ID
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#define V_PCH_SCS_SDCARD_DEVICE_ID 0x9D2D
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//
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// SCS Devices PCI Config Space Registers
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//
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#define R_PCH_SCS_DEV_PCS 0x84 ///< PME Control Status
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#define B_PCH_SCS_DEV_PCS_PMESTS BIT15 ///< PME Status
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#define B_PCH_SCS_DEV_PCS_PMEEN BIT8 ///< PME Enable
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#define B_PCH_SCS_DEV_PCS_NSS BIT3 ///< No Soft Reset
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#define B_PCH_SCS_DEV_PCS_PS (BIT1 | BIT0) ///< Power State
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#define B_PCH_SCS_DEV_PCS_PS_D3HOT (BIT1 | BIT0) ///< Power State: D3Hot State
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#define R_PCH_SCS_DEV_PG_CONFIG 0xA2 ///< PG Config
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#define B_PCH_SCS_DEV_PG_CONFIG_SE BIT3 ///< Sleep Enable
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#define B_PCH_SCS_DEV_PG_CONFIG_PGE BIT2 ///< PG Enable
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#define B_PCH_SCS_DEV_PG_CONFIG_I3E BIT1 ///< I3 Enable
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#define B_PCH_SCS_DEV_PG_CONFIG_PMCRE BIT0 ///< PMC Request Enable
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#define V_PCH_SCS_DEV_BAR0_SIZE 0x1000 ///< BAR0 size
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//
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// SCS Devices MMIO Space Register
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//
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#define R_PCH_SCS_DEV_MEM_DMAADR 0x00
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#define R_PCH_SCS_DEV_MEM_BLKSZ 0x04
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#define R_PCH_SCS_DEV_MEM_BLKCNT 0x06
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#define R_PCH_SCS_DEV_MEM_CMDARG 0x08
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#define R_PCH_SCS_DEV_MEM_XFRMODE 0x0C
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#define B_PCH_SCS_DEV_MEM_XFRMODE_DMA_EN BIT0
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#define B_PCH_SCS_DEV_MEM_XFRMODE_BLKCNT_EN BIT1
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#define B_PCH_SCS_DEV_MEM_XFRMODE_AUTOCMD_EN_MASK (BIT2 | BIT3)
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#define V_PCH_SCS_DEV_MEM_XFRMODE_AUTOCMD12_EN 1
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#define B_PCH_SCS_DEV_MEM_XFRMODE_DATA_TRANS_DIR BIT4 ///< 1: Read (Card to Host), 0: Write (Host to Card)
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#define B_PCH_SCS_DEV_MEM_XFRMODE_MULTI_SINGLE_BLK BIT5 ///< 1: Multiple Block, 0: Single Block
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#define R_PCH_SCS_DEV_MEM_SDCMD 0x0E
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#define B_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_MASK (BIT0 | BIT1)
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#define V_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_NO_RESP 0
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#define V_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_RESP136 1
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#define V_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_RESP48 2
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#define V_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_RESP48_CHK 3
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#define B_PCH_SCS_DEV_MEM_SDCMD_CMD_CRC_CHECK_EN BIT3
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#define B_PCH_SCS_DEV_MEM_SDCMD_CMD_INDEX_CHECK_EN BIT4
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#define B_PCH_SCS_DEV_MEM_SDCMD_DATA_PRESENT_SEL BIT5
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#define R_PCH_SCS_DEV_MEM_RESP 0x10
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#define R_PCH_SCS_DEV_MEM_BUFDATAPORT 0x20
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#define R_PCH_SCS_DEV_MEM_PSTATE 0x24
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#define B_PCH_SCS_DEV_MEM_PSTATE_DAT0 BIT20
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#define R_PCH_SCS_DEV_MEM_PWRCTL 0x29
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#define R_PCH_SCS_DEV_MEM_CLKCTL 0x2C
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#define R_PCH_SCS_DEV_MEM_TIMEOUT_CTL 0x2E ///< Timeout Control
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#define B_PCH_SCS_DEV_MEM_TIMEOUT_CTL_DTCV 0x0F ///< Data Timeout Counter Value
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#define R_PCH_SCS_DEV_MEM_SWRST 0x2F
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#define B_PCH_SCS_DEV_MEM_SWRST_CMDLINE BIT1
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#define B_PCH_SCS_DEV_MEM_SWRST_DATALINE BIT2
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#define R_PCH_SCS_DEV_MEM_NINTSTS 0x30
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#define B_PCH_SCS_DEV_MEM_NINTSTS_MASK 0xFFFF
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#define B_PCH_SCS_DEV_MEM_NINTSTS_CLEAR_MASK 0x60FF
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#define B_PCH_SCS_DEV_MEM_NINTSTS_CMD_COMPLETE BIT0
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#define B_PCH_SCS_DEV_MEM_NINTSTS_TRANSFER_COMPLETE BIT1
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#define B_PCH_SCS_DEV_MEM_NINTSTS_DMA_INTERRUPT BIT3
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#define B_PCH_SCS_DEV_MEM_NINTSTS_BUF_READ_READY_INTR BIT5
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#define R_PCH_SCS_DEV_MEM_ERINTSTS 0x32
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#define B_PCH_SCS_DEV_MEM_ERINTSTS_MASK 0x13FF
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#define B_PCH_SCS_DEV_MEM_ERINTSTS_CLEAR_MASK 0x13FF
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#define R_PCH_SCS_DEV_MEM_NINTEN 0x34
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#define B_PCH_SCS_DEV_MEM_NINTEN_MASK 0x7FFF
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#define R_PCH_SCS_DEV_MEM_ERINTEN 0x36
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#define B_PCH_SCS_DEV_MEM_ERINTEN_MASK 0x13FF
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#define R_PCH_SCS_DEV_MEM_NINTSIGNEN 0x38
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#define B_PCH_SCS_DEV_MEM_NINTSIGNEN_MASK 0x7FFF
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#define R_PCH_SCS_DEV_MEM_ERINTSIGNEN 0x3A
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#define B_PCH_SCS_DEV_MEM_ERINTSIGNEN_MASK 0x13FF
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#define R_PCH_SCS_DEV_MEM_HOST_CTL2 0x3E
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#define B_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_MASK (BIT0 | BIT1 | BIT2)
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#define V_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_HS400 5
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#define V_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_DDR50 4
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#define V_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_SDR104 3
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#define V_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_SDR25 1
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#define R_PCH_SCS_DEV_MEM_CAP1 0x40
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#define R_PCH_SCS_DEV_MEM_CAP2 0x44
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#define B_PCH_SCS_DEV_MEM_CAP2_HS400_SUPPORT BIT31
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#define B_PCH_SCS_DEV_MEM_CAP2_SDR104_SUPPORT BIT1
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#define R_PCH_SCS_DEV_MEM_CESHC2 0x3C ///< Auto CMD12 Error Status Register & Host Control 2
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#define B_PCH_SCS_DEV_MEM_CESHC2_ASYNC_INT BIT30 ///< Asynchronous Interrupt Enable
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#define R_PCH_SCS_DEV_MEM_CAP_BYPASS_CONTROL 0x810
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#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_CONTROL_EN 0x5A
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#define R_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1 0x814
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#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_EMMC_DEFAULTS 0x3C80EB1E
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#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SDIO_DEFAULTS 0x1C80EF1E
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#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SDCARD_DEFAULTS 0x1C80E75C
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#define B_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_HS400 BIT29
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#define B_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMEOUT_CLK_FREQ (BIT27 | BIT26 | BIT25 | BIT24 | BIT23 | BIT22)
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#define N_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMEOUT_CLK_FREQ 22
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#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMEOUT_CLK_FREQ 0x1
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#define B_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMER_COUNT (BIT20 | BIT19 | BIT18 | BIT17)
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#define N_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMER_COUNT 17
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#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMER_COUNT 0x8
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#define B_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SLOT_TYPE (BIT12 | BIT11)
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#define N_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SLOT_TYPE 11
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#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SLOT_TYPE_EMBEDDED 0x1
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#define R_PCH_SCS_DEV_MEM_CAP_BYPASS_REG2 0x818
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#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG2_EMMC_DEFAULTS 0x040040C8
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#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG2_SDIO_DEFAULTS 0x040000C8
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#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG2_SDCARD_DEFAULTS 0x040000C8
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#define R_PCH_SCS_DEV_MEM_TX_CMD_DLL_CNTL1 0x820
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#define R_PCH_SCS_DEV_MEM_TX_CMD_DLL_CNTL2 0x80C
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#define R_PCH_SCS_DEV_MEM_TX_DATA_DLL_CNTL1 0x824
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#define R_PCH_SCS_DEV_MEM_TX_DATA_DLL_CNTL2 0x828
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#define R_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL1 0x82C
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#define R_PCH_SCS_DEV_MEM_RX_STROBE_DLL_CNTL 0x830
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#define R_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2 0x834
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#define N_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2_CLKSRC_RX 16
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#define V_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2_CLKSRC_RX_CLK_AUTO 0x2
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#define V_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2_CLKSRC_RX_CLK_BEFORE 0x1
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#define V_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2_CLKSRC_RX_CLK_AFTER 0x0
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//
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// SCS Private Configuration Space Registers
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//
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#define R_PCH_PCR_SCS_IOSFCTL 0x00 ///< IOSF Control
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#define B_PCH_PCR_SCS_IOSFCTL_NSNPDIS BIT7 ///< Non-Snoop Disable
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#define B_PCH_PCR_SCS_IOSFCTL_MAX_RD_PEND (BIT3 | BIT2 | BIT1 | BIT0) ///< Max upstream pending reads
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#define R_PCH_PCR_SCS_OCPCTL 0x10 ///< OCP Control
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#define B_PCH_PCR_SCS_OCPCTL_NPEN BIT0 ///< Downstream non-posted memory write capability
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#define R_PCH_PCR_SCS_PMCTL 0x1D0 ///< Power Management Control
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#define R_PCH_PCR_SCS_PCICFGCTR_EMMC 0x200 ///< PCI Configuration Control 1 - eMMC
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#define R_PCH_PCR_SCS_PCICFGCTR_SDIO 0x204 ///< PCI Configuration Control 2 - SDIO
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#define R_PCH_PCR_SCS_PCICFGCTR_SDCARD 0x208 ///< PCI Configuration Control 3 - SD Card
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#define B_PCH_PCR_SCS_PCICFGCTR_PCI_IRQ 0x0FF00000 ///< PCI IRQ number
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#define N_PCH_PCR_SCS_PCICFGCTR_PCI_IRQ 20
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#define B_PCH_PCR_SCS_PCICFGCTR_ACPI_IRQ 0x000FF000 ///< ACPI IRQ number
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#define N_PCH_PCR_SCS_PCICFGCTR_ACPI_IRQ 12
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#define B_PCH_PCR_SCS_PCICFGCTR_IPIN1 (BIT11 | BIT10 | BIT9 | BIT8) ///< Interrupt Pin
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#define N_PCH_PCR_SCS_PCICFGCTR_IPIN1 8
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#define B_PCH_PCR_SCS_PCICFGCTR_BAR1DIS BIT7 ///< BAR 1 Disable
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#define B_PCH_PCR_SCS_PCICFGCTR_PS 0x7C ///< PME Support
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#define B_PCH_PCR_SCS_PCICFGCTR_ACPI_INT_EN BIT1 ///< ACPI Interrupt Enable
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#define B_PCH_PCR_SCS_PCICFGCTR_PCI_CFG_DIS BIT0 ///< PCI Configuration Space Disable
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#define R_PCH_PCR_SCS_GPPRVRW1 0x600 ///< Clock Gating Control
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#define R_PCH_PCR_SCS_GPPRVRW2 0x604 ///< Host Controller Disable
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#define B_PCH_PCR_SCS_GPPRVRW2_EMMC_DIS BIT1 ///< eMMC Host Controller Disable
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#define B_PCH_PCR_SCS_GPPRVRW2_SDIO_SDCARD_DIS BIT2 ///< 1: SDIO Host Controller Disable, 0: SDCARD Host Controller Disable
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#define R_PCH_PCR_SCS_GPPRVRW6 0x614 ///< 1.8V Signal Select Delay Control
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#define V_PCH_PCR_SCS_GPPRVRW6_1P8_SEL_DELAY 0x7F ///< Rcomp SDCARD 10ms delay during switch
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#endif
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