/** @file
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Register definition for PSTH component
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Conventions:
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- Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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- In general, PCH registers are denoted by "_PCH_" in register names
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- Registers / bits that are different between PCH generations are denoted by
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"_PCH_[generation_name]_" in register/bit names.
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- Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
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Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
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e.g., "_PCH_H_", "_PCH_LP_"
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Registers / bits names without _H_ or _LP_ apply for both H and LP.
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- Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
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at the end of the register/bit names
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- Registers / bits of new devices introduced in a PCH generation will be just named
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as "_PCH_" without [generation_name] inserted.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_PSTH_H_
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#define _PCH_REGS_PSTH_H_
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//
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// Private chipset regsiter (Memory space) offset definition
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// The PCR register defines is used for PCR MMIO programming and PCH SBI programming as well.
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//
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//
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// PSTH and IO Trap PCRs (PID:PSTH)
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//
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#define R_PCH_PCR_PSTH_PSTHCTL 0x1D00 ///< PSTH control register
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#define B_PCH_PCR_PSTH_PSTHIOSFPTCGE BIT2 ///< PSTH IOSF primary trunk clock gating enable
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#define B_PCH_PCR_PSTH_PSTHIOSFSTCGE BIT1 ///< PSTH IOSF sideband trunk clock gating enable
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#define B_PCH_PCR_PSTH_PSTHDCGE BIT0 ///< PSTH dynamic clock gating enable
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#define R_PCH_PCR_PSTH_TRPST 0x1E00 ///< Trap status regsiter
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#define B_PCH_PCR_PSTH_TRPST_CTSS 0x0000000F ///< Cycle Trap SMI# Status mask
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#define R_PCH_PCR_PSTH_TRPC 0x1E10 ///< Trapped cycle
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#define B_PCH_PCR_PSTH_TRPC_RW BIT24 ///< Read/Write#: 1=Read, 0=Write
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#define B_PCH_PCR_PSTH_TRPC_AHBE 0x00000000000F0000 ///< Active high byte enables
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#define B_PCH_PCR_PSTH_TRPC_IOA 0x000000000000FFFC ///< Trap cycle I/O address
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#define R_PCH_PCR_PSTH_TRPD 0x1E18 ///< Trapped write data
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#define B_PCH_PCR_PSTH_TRPD_IOD 0x00000000FFFFFFFF ///< Trap cycle I/O data
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#define R_PCH_PCR_PSTH_TRPREG0 0x1E80 ///< IO Tarp 0 register
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#define R_PCH_PCR_PSTH_TRPREG1 0x1E88 ///< IO Tarp 1 register
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#define R_PCH_PCR_PSTH_TRPREG2 0x1E90 ///< IO Tarp 2 register
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#define R_PCH_PCR_PSTH_TRPREG3 0x1E98 ///< IO Tarp 3 register
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#define B_PCH_PCR_PSTH_TRPREG_RWM BIT17 ///< 49 - 32 for 32 bit access, Read/Write mask
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#define B_PCH_PCR_PSTH_TRPREG_RWIO BIT16 ///< 48 - 32 for 32 bit access, Read/Write#, 1=Read, 0=Write
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#define N_PCH_PCR_PSTH_TRPREG_RWIO 16 ///< 48 - 32 for 32 bit access, 16bit shift for Read/Write field
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#define N_PCH_PCR_PSTH_TRPREG_BEM (36 - 32)
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#define B_PCH_PCR_PSTH_TRPREG_BEM 0x000000F000000000 ///< Byte enable mask
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#define B_PCH_PCR_PSTH_TRPREG_BE 0x0000000F00000000 ///< Byte enable
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#define B_PCH_PCR_PSTH_TRPREG_AM 0x0000000000FC0000 ///< IO Address mask
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#define B_PCH_PCR_PSTH_TRPREG_AD 0x000000000000FFFC ///< IO Address
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#define B_PCH_PCR_PSTH_TRPREG_TSE BIT0 ///< Trap and SMI# Enable
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#endif
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