/** @file
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Register names for PCH private chipset register
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Conventions:
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- Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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- In general, PCH registers are denoted by "_PCH_" in register names
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- Registers / bits that are different between PCH generations are denoted by
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"_PCH_[generation_name]_" in register/bit names.
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- Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
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Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
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e.g., "_PCH_H_", "_PCH_LP_"
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Registers / bits names without _H_ or _LP_ apply for both H and LP.
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- Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
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at the end of the register/bit names
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- Registers / bits of new devices introduced in a PCH generation will be just named
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as "_PCH_" without [generation_name] inserted.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_PCR_H_
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#define _PCH_REGS_PCR_H_
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///
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/// Definition for PCR base address (defined in PchReservedResources.h)
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///
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//#define PCH_PCR_BASE_ADDRESS 0xFD000000
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//#define PCH_PCR_MMIO_SIZE 0x01000000
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/**
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Definition for PCR address
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The PCR address is used to the PCR MMIO programming
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**/
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#define PCH_PCR_ADDRESS(Pid, Offset) (PCH_PCR_BASE_ADDRESS | ((UINT8)(Pid) << 16) | (UINT16)(Offset))
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/**
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PCH PCR boot script accessing macro
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Those macros are only available for DXE phase.
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**/
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#define PCH_PCR_BOOT_SCRIPT_WRITE(Width, Pid, Offset, Count, Buffer) \
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S3BootScriptSaveMemWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), Count, Buffer); \
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S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS (Pid, Offset), Buffer, Buffer, 1, 1);
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#define PCH_PCR_BOOT_SCRIPT_READ_WRITE(Width, Pid, Offset, DataOr, DataAnd) \
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S3BootScriptSaveMemReadWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), DataOr, DataAnd); \
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S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS (Pid, Offset), DataOr, DataOr, 1, 1);
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/**
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Definition for SBI PID
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The PCH_SBI_PID defines the PID for PCR MMIO programming and PCH SBI programming as well.
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**/
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#define PID_DMI 0xEF
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#define PID_ESPISPI 0xEE
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#define PID_OPIPHY 0xEC
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#define PID_MODPHY0 0xEA
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#define PID_MODPHY1 0xE9
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#define PID_OTG 0xE5
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#define PID_SPF 0xC9 // Available only in KBL PCH H
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#define PID_SPE 0xE4 // Reserved in SKL PCH LP
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#define PID_SPD 0xE3 // Reserved in SKL PCH LP
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#define PID_SPC 0xE2
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#define PID_SPB 0xE1
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#define PID_SPA 0xE0
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#define PID_ICC 0xDC
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#define PID_DSP 0xD7
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#define PID_FIA 0xCF
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#define PID_SERIALIO 0xCB
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#define PID_USB2 0xCA
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#define PID_LPC 0xC7
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#define PID_SMB 0xC6
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#define PID_ITSS 0xC4
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#define PID_RTC 0xC3
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#define PID_SCS 0xC0 // Reserved in SKL PCH H
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#define PID_ISHBR 0xBF
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#define PID_ISH 0xBE
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#define PID_PSF4 0xBD
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#define PID_PSF3 0xBC
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#define PID_PSF2 0xBB
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#define PID_PSF1 0xBA
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#define PID_DCI 0xB8
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#define PID_MMP0 0xB0 // for SKL-LP only
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#define PID_MODPHY4 0xB0 // for KBL-H only
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#define PID_GPIOCOM0 0xAF
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#define PID_GPIOCOM1 0xAE
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#define PID_GPIOCOM2 0xAD
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#define PID_GPIOCOM3 0xAC
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#define PID_CAM_FLS 0xAA
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#define PID_MODPHY2 0xA9
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#define PID_MODPHY3 0xA8
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#define PID_CAM_CHC 0xA1
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#define PID_CSME12 0x9C
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#define PID_CSME0 0x90
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#define PID_CSME_PSF 0x8F
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#define PID_PSTH 0x89
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typedef UINT8 PCH_SBI_PID;
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#endif
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