/** @file
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Register names for ITSS
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Conventions:
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- Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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- In general, PCH registers are denoted by "_PCH_" in register names
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- Registers / bits that are different between PCH generations are denoted by
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"_PCH_[generation_name]_" in register/bit names.
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- Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
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Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
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e.g., "_PCH_H_", "_PCH_LP_"
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Registers / bits names without _H_ or _LP_ apply for both H and LP.
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- Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
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at the end of the register/bit names
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- Registers / bits of new devices introduced in a PCH generation will be just named
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as "_PCH_" without [generation_name] inserted.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_ITSS_H_
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#define _PCH_REGS_ITSS_H_
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//
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// ITSS PCRs (PID:ITSS)
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//
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#define R_PCH_PCR_ITSS_PIRQA_ROUT 0x3100 ///< PIRQA Routing Control register
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#define R_PCH_PCR_ITSS_PIRQB_ROUT 0x3101 ///< PIRQB Routing Control register
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#define R_PCH_PCR_ITSS_PIRQC_ROUT 0x3102 ///< PIRQC Routing Control register
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#define R_PCH_PCR_ITSS_PIRQD_ROUT 0x3103 ///< PIRQD Routing Control register
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#define R_PCH_PCR_ITSS_PIRQE_ROUT 0x3104 ///< PIRQE Routing Control register
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#define R_PCH_PCR_ITSS_PIRQF_ROUT 0x3105 ///< PIRQF Routing Control register
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#define R_PCH_PCR_ITSS_PIRQG_ROUT 0x3106 ///< PIRQG Routing Control register
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#define R_PCH_PCR_ITSS_PIRQH_ROUT 0x3107 ///< PIRQH Routing Control register
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#define B_PCH_PCR_ITSS_PIRQX_ROUT_REN 0x80 ///< Interrupt Routing Enable
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#define B_PCH_PCR_ITSS_PIRQX_ROUT_IR 0x0F ///< IRQ Routng
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#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_3 0x03 ///< Route PIRQx to IRQ3
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#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_4 0x04 ///< Route PIRQx to IRQ4
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#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_5 0x05 ///< Route PIRQx to IRQ5
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#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_6 0x06 ///< Route PIRQx to IRQ6
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#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_7 0x07 ///< Route PIRQx to IRQ7
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#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_9 0x09 ///< Route PIRQx to IRQ9
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#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_10 0x0A ///< Route PIRQx to IRQ10
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#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_11 0x0B ///< Route PIRQx to IRQ11
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#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_12 0x0C ///< Route PIRQx to IRQ12
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#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_14 0x0E ///< Route PIRQx to IRQ14
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#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_15 0x0F ///< Route PIRQx to IRQ15
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#define R_PCH_PCR_ITSS_PIR0 0x3140 ///< PCI Interrupt Route 0
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#define R_PCH_PCR_ITSS_PIR1 0x3142 ///< PCI Interrupt Route 1
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#define R_PCH_PCR_ITSS_PIR2 0x3144 ///< PCI Interrupt Route 2
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#define R_PCH_PCR_ITSS_PIR3 0x3146 ///< PCI Interrupt Route 3
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#define R_PCH_PCR_ITSS_PIR4 0x3148 ///< PCI Interrupt Route 4
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#define R_PCH_PCR_ITSS_PIR5 0x314A ///< PCI Interrupt Route 5
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#define R_PCH_PCR_ITSS_PIR6 0x314C ///< PCI Interrupt Route 6
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#define R_PCH_PCR_ITSS_PIR7 0x314E ///< PCI Interrupt Route 7
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#define R_PCH_PCR_ITSS_PIR8 0x3150 ///< PCI Interrupt Route 8
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#define R_PCH_PCR_ITSS_PIR9 0x3152 ///< PCI Interrupt Route 9
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#define R_PCH_PCR_ITSS_PIR10 0x3154 ///< PCI Interrupt Route 10
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#define R_PCH_PCR_ITSS_PIR11 0x3156 ///< PCI Interrupt Route 11
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#define R_PCH_PCR_ITSS_PIR12 0x3158 ///< PCI Interrupt Route 12
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#define R_PCH_PCR_ITSS_GIC 0x31FC ///< General Interrupt Control
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#define B_PCH_PCR_ITSS_GIC_MAX_IRQ_24 BIT9 ///< Max IRQ entry size, 1 = 24 entry size, 0 = 120 entry size
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#define B_PCH_PCR_ITSS_GIC_AME BIT17 ///< Alternate Access Mode Enable
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#define B_PCH_PCR_ITSS_GIC_SPS BIT16 ///< Shutdown Policy Select
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#define R_PCH_PCR_ITSS_IPC0 0x3200 ///< Interrupt Polarity Control 0
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#define R_PCH_PCR_ITSS_IPC1 0x3204 ///< Interrupt Polarity Control 1
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#define R_PCH_PCR_ITSS_IPC2 0x3208 ///< Interrupt Polarity Control 2
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#define R_PCH_PCR_ITSS_IPC3 0x320C ///< Interrupt Polarity Control 3
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#define R_PCH_PCR_ITSS_ITSSPRC 0x3300 ///< ITSS Power Reduction Control
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#define B_PCH_PCR_ITSS_ITSSPRC_PGCBDCGE BIT4 ///< PGCB Dynamic Clock Gating Enable
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#define B_PCH_PCR_ITSS_ITSSPRC_HPETDCGE BIT3 ///< HPET Dynamic Clock Gating Enable
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#define B_PCH_PCR_ITSS_ITSSPRC_8254CGE BIT2 ///< 8254 Static Clock Gating Enable
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#define B_PCH_PCR_ITSS_ITSSPRC_IOSFICGE BIT1 ///< IOSF-Sideband Interface Clock Gating Enable
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#define B_PCH_PCR_ITSS_ITSSPRC_ITSSCGE BIT0 ///< ITSS Clock Gate Enable
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#define R_PCH_PCR_ITSS_MMC 0x3334 ///< Master Message Control
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#define B_PCH_PCR_ITSS_MMC_MSTRMSG_EN BIT0 ///< Master Message Enable
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#endif
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