/** @file
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Register names for PCH Integrated Sensor Hub (ISH3.0)
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Conventions:
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- Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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- In general, PCH registers are denoted by "_PCH_" in register names
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- Registers / bits that are different between PCH generations are denoted by
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"_PCH_[generation_name]_" in register/bit names.
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- Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
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Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
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e.g., "_PCH_H_", "_PCH_LP_"
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Registers / bits names without _H_ or _LP_ apply for both H and LP.
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- Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
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at the end of the register/bit names
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- Registers / bits of new devices introduced in a PCH generation will be just named
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as "_PCH_" without [generation_name] inserted.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_ISH_H_
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#define _PCH_REGS_ISH_H_
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//
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// ISH Controller Registers (D19:F0)
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//
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// PCI Configuration Space Registers
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#define PCI_DEVICE_NUMBER_PCH_ISH 19
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#define PCI_FUNCTION_NUMBER_PCH_ISH 0
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#define R_PCH_ISH_BAR0_LOW 0x10
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#define R_PCH_ISH_BAR0_HIGH 0x14
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#define V_PCH_ISH_BAR0_SIZE 0x100000
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#define N_PCH_ISH_BAR0_ALIGNMENT 20
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#define R_PCH_ISH_BAR1_LOW 0x18
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#define R_PCH_ISH_BAR1_HIGH 0x1C
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#define V_PCH_ISH_BAR1_SIZE 0x1000
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#define N_PCH_ISH_BAR1_ALIGNMENT 12
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//
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// ISH Private Configuration Space Registers (IOSF2OCP)
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// (PID:ISH)
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//
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#define R_PCH_PCR_ISH_PMCTL 0x1D0 ///< Power Management
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#define R_PCH_PCR_ISH_PCICFGCTRL 0x200 ///< PCI Configuration Control
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#define B_PCH_PCR_ISH_PCICFGCTR_PCI_IRQ 0x0FF00000 ///< PCI IRQ number
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#define N_PCH_PCR_ISH_PCICFGCTR_PCI_IRQ 20
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#define B_PCH_PCR_ISH_PCICFGCTR_ACPI_IRQ 0x000FF000 ///< ACPI IRQ number
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#define N_PCH_PCR_ISH_PCICFGCTR_ACPI_IRQ 12
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#define B_PCH_PCR_ISH_PCICFGCTR_IPIN1 (BIT11 | BIT10 | BIT9 | BIT8) ///< Interrupt Pin
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#define N_PCH_PCR_ISH_PCICFGCTR_IPIN1 8
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#define B_PCH_PCR_ISH_PCICFGCTRL_BAR1DIS BIT7 ///< BAR1 Disable
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//
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// Number of pins used by ISH controllers
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//
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#define PCH_ISH_PINS_PER_I2C_CONTROLLER 2
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#define PCH_ISH_PINS_PER_UART_CONTROLLER 4
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#define PCH_ISH_PINS_PER_SPI_CONTROLLER 4
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#endif
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