/** @file
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Register names for PCH High Definition Audio device.
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Conventions:
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- Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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- In general, PCH registers are denoted by "_PCH_" in register names
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- Registers / bits that are different between PCH generations are denoted by
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"_PCH_[generation_name]_" in register/bit names.
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- Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
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Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
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e.g., "_PCH_H_", "_PCH_LP_"
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Registers / bits names without _H_ or _LP_ apply for both H and LP.
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- Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
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at the end of the register/bit names
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- Registers / bits of new devices introduced in a PCH generation will be just named
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as "_PCH_" without [generation_name] inserted.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_HDA_H_
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#define _PCH_REGS_HDA_H_
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//
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// HD-A Controller Registers (D31:F3)
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//
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// PCI Configuration Space Registers
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//
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#define PCI_DEVICE_NUMBER_PCH_HDA 31
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#define PCI_FUNCTION_NUMBER_PCH_HDA 3
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#define R_PCH_HDA_PI 0x09
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#define V_PCH_HDA_PI_ADSP_UAA 0x80
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#define R_PCH_HDA_SCC 0x0A
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#define V_PCH_HDA_SCC_ADSP 0x01
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#define R_PCH_HDA_HDALBA 0x10
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#define B_PCH_HDA_HDALBA_LBA 0xFFFFC000
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#define V_PCH_HDA_HDBAR_SIZE (1 << 14)
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#define R_PCH_HDA_HDAUBA 0x14
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#define B_PCH_HDA_HDAUBA_UBA 0xFFFFFFFF
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#define R_PCH_HDA_CGCTL 0x48
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#define B_PCH_HDA_CGCTL_SROTCGE BIT18
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#define B_PCH_HDA_CGCTL_MISCBDCGE BIT6
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#define R_PCH_HDA_PC 0x52
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#define V_PCH_HDA_PC_PMES 0x18
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#define N_PCH_HDA_PC_PMES 11
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#define R_PCH_HDA_PCS 0x54
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#define B_PCH_HDA_PCS_PMEE BIT8
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#define B_PCH_HDA_PCS_PS (BIT1 | BIT0)
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#define R_PCH_HDA_MMC 0x62
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#define B_PCH_HDA_MMC_ME BIT0
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#define R_PCH_HDA_DEVC 0x78
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#define B_PCH_HDA_DEVC_NSNPEN BIT11
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#define R_PCH_HDA_SEM1 0xC0
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#define B_PCH_HDA_SEM1_LFLCS BIT24
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#define B_PCH_HDA_SEM1_BLKC3DIS BIT17
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#define B_PCH_HDA_SEM1_TMODE BIT12
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#define B_PCH_HDA_SEM1_FIFORDYSEL (BIT10 | BIT9)
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#define R_PCH_HDA_SEM2 0xC4
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#define B_PCH_HDA_SEM2_BSMT (BIT27 | BIT26)
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#define V_PCH_HDA_SEM2_BSMT 0x1
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#define N_PCH_HDA_SEM2_BSMT 26
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#define B_PCH_HDA_SEM2_VC0PSNR BIT24
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#define B_PCH_HDA_SEM2_DUM BIT23
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#define R_PCH_HDA_SEM3L 0xC8
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#define B_PCH_HDA_SEM3L_ISL1EXT2 (BIT21 | BIT20)
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#define V_PCH_HDA_SEM3L_ISL1EXT2 0x2
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#define N_PCH_HDA_SEM3L_ISL1EXT2 20
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#define R_PCH_HDA_SEM4L 0xD0
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#define B_PCH_HDA_SEM4L_OSL1EXT2 (BIT21 | BIT20)
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#define V_PCH_HDA_SEM4L_OSL1EXT2 0x3
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#define N_PCH_HDA_SEM4L_OSL1EXT2 20
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//
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// Memory Space Registers
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//
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//
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// Resides in 'HD Audio Global Registers' (0000h)
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//
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#define R_PCH_HDABA_GCAP 0x00
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#define R_PCH_HDABA_GCTL 0x08
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#define B_PCH_HDABA_GCTL_CRST BIT0
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#define R_PCH_HDABA_OUTPAY 0x04
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#define R_PCH_HDABA_INPAY 0x06
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#define V_PCH_HDABA_INPAY_DEFAULT 0x1C
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#define R_PCH_HDABA_WAKEEN 0x0C
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#define B_PCH_HDABA_WAKEEN_SDI_3 BIT3
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#define B_PCH_HDABA_WAKEEN_SDI_2 BIT2
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#define B_PCH_HDABA_WAKEEN_SDI_1 BIT1
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#define B_PCH_HDABA_WAKEEN_SDI_0 BIT0
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#define R_PCH_HDABA_WAKESTS 0x0E
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#define B_PCH_HDABA_WAKESTS_SDIN3 BIT3
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#define B_PCH_HDABA_WAKESTS_SDIN2 BIT2
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#define B_PCH_HDABA_WAKESTS_SDIN1 BIT1
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#define B_PCH_HDABA_WAKESTS_SDIN0 BIT0
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//
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// Resides in 'HD Audio Controller Registers' (0030h)
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//
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#define R_PCH_HDABA_IC 0x60
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#define R_PCH_HDABA_IR 0x64
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#define R_PCH_HDABA_ICS 0x68
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#define B_PCH_HDABA_ICS_IRV BIT1
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#define B_PCH_HDABA_ICS_ICB BIT0
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//
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// Resides in 'HD Audio Processing Pipe Capability Structure' (0800h)
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//
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#define R_PCH_HDABA_PPC 0x0800 // Processing Pipe Capability Structure (Memory Space, offset 0800h)
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#define R_PCH_HDABA_PPCTL (R_PCH_HDABA_PPC + 0x04)
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#define B_PCH_HDABA_PPCTL_GPROCEN BIT30
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//
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// Resides in 'HD Audio Multiple Links Capability Structure' (0C00h)
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//
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#define V_PCH_HDA_HDALINK_INDEX 0
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#define V_PCH_HDA_IDISPLINK_INDEX 1
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#define R_PCH_HDABA_MLC 0x0C00 // Multiple Links Capability Structure (Memory Space, offset 0C00h)
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#define R_PCH_HDABA_LCTLX(x) (R_PCH_HDABA_MLC + (0x40 + (0x40 * (x)) + 0x04)) // x - Link index: 0 - HDA Link, 1 - iDisp Link
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#define B_PCH_HDABA_LCTLX_CPA BIT23
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#define B_PCH_HDABA_LCTLX_SPA BIT16
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#define N_PCH_HDABA_LCTLX_SCF 0
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#define V_PCH_HDABA_LCTLX_SCF_6MHZ 0x0
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#define V_PCH_HDABA_LCTLX_SCF_12MHZ 0x1
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#define V_PCH_HDABA_LCTLX_SCF_24MHZ 0x2
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#define V_PCH_HDABA_LCTLX_SCF_48MHZ 0x3
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#define V_PCH_HDABA_LCTLX_SCF_96MHZ 0x4
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//
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// Resides in 'HD Audio Vendor Specific Registers' (1000h)
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//
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#define R_PCH_HDABA_LTRC 0x1048
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#define V_PCH_HDABA_LTRC_GB 0x29
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#define N_PCH_HDABA_LTRC_GB 0
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#define R_PCH_HDABA_PCE 0x104B
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#define B_PCH_HDABA_PCE_D3HE BIT2
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//
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// Private Configuration Space Registers
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//
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//
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// Resides in IOSF & Fabric Configuration Registers (000h)
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//
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#define R_PCH_PCR_HDA_TTCCFG 0xE4
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#define B_PCH_PCR_HDA_TTCCFG_HCDT BIT1
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//
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// Resides in PCI & Codec Configuration Registers (500h)
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//
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#define R_PCH_PCR_HDA_PCICDCCFG 0x500 // PCI & Codec Configuration Registers (PCR, offset 500h)
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#define B_PCH_PCR_HDA_PCICDCCFG_ACPIIN 0x0000FF00
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#define N_PCH_PCR_HDA_PCICDCCFG_ACPIIN 8
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#define R_PCH_PCR_HDA_FNCFG (R_PCH_PCR_HDA_PCICDCCFG + 0x30)
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#define B_PCH_PCR_HDA_FNCFG_PGD BIT5
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#define B_PCH_PCR_HDA_FNCFG_BCLD BIT4
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#define B_PCH_PCR_HDA_FNCFG_CGD BIT3
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#define B_PCH_PCR_HDA_FNCFG_ADSPD BIT2
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#define B_PCH_PCR_HDA_FNCFG_HDASD BIT0
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#define R_PCH_PCR_HDA_CDCCFG (R_PCH_PCR_HDA_PCICDCCFG + 0x34)
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#define B_PCH_PCR_HDA_CDCCFG_DIS_SDIN2 BIT2
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//
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// Resides in Power Management & EBB Configuration Registers (600h)
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//
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#define R_PCH_PCR_HDA_PWRMANCFG 0x600 // Power Management & EBB Configuration Registers (PCR, offset 600h)
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#define R_PCH_PCR_HDA_APLLP0 (R_PCH_PCR_HDA_PWRMANCFG + 0x10)
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#define V_PCH_PCR_HDA_APLLP0 0xFC1E0000
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#define R_PCH_PCR_HDA_APLLP1 (R_PCH_PCR_HDA_PWRMANCFG + 0x14)
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#define V_PCH_PCR_HDA_APLLP1 0x00001E00
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#define R_PCH_PCR_HDA_APLLP2 (R_PCH_PCR_HDA_PWRMANCFG + 0x18)
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#define V_PCH_PCR_HDA_APLLP2 0x0000011D
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#define R_PCH_PCR_HDA_IOBCTL (R_PCH_PCR_HDA_PWRMANCFG + 0x1C)
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#define B_PCH_PCR_HDA_IOBCTL_OSEL (BIT9 | BIT8)
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#define V_PCH_PCR_HDA_IOBCTL_OSEL_HDALINK 0
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#define V_PCH_PCR_HDA_IOBCTL_OSEL_HDALINK_I2S 1
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#define V_PCH_PCR_HDA_IOBCTL_OSEL_I2S 3
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#define N_PCH_PCR_HDA_IOBCTL_OSEL 8
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#define B_PCH_PCR_HDA_IOBCTL_VSEL BIT1
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#define R_PCH_PCR_HDA_PTDC (R_PCH_PCR_HDA_PWRMANCFG + 0x28)
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#define B_PCH_PCR_HDA_PTDC_SRMIW (BIT6 | BIT5 | BIT4)
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#define V_PCH_PCR_HDA_PTDC_SRMIW_256XTAL 0x6
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#define N_PCH_PCR_HDA_PTDC_SRMIW 4
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#endif
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