/** @file
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Register definition for FIA component
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Conventions:
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- Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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- In general, PCH registers are denoted by "_PCH_" in register names
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- Registers / bits that are different between PCH generations are denoted by
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"_PCH_[generation_name]_" in register/bit names.
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- Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
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Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
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e.g., "_PCH_H_", "_PCH_LP_"
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Registers / bits names without _H_ or _LP_ apply for both H and LP.
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- Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
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at the end of the register/bit names
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- Registers / bits of new devices introduced in a PCH generation will be just named
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as "_PCH_" without [generation_name] inserted.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_FIA_H_
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#define _PCH_REGS_FIA_H_
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//
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// Private chipset regsiter (Memory space) offset definition
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// The PCR register defines is used for PCR MMIO programming and PCH SBI programming as well.
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//
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//
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// PID:FIA
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//
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#define SKL_PCH_MAX_FIA_DRCRM 3
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#define KBL_PCH_MAX_FIA_DRCRM 4
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#define PCH_MAX_FIA_DRCRM KBL_PCH_MAX_FIA_DRCRM
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#define R_PCH_PCR_FIA_CC 0
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#define B_PCH_PCR_FIA_CC_SRL BIT31
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#define B_PCH_PCR_FIA_CC_PTOCGE BIT17
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#define B_PCH_PCR_FIA_CC_OSCDCGE BIT16
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#define B_PCH_PCR_FIA_CC_SCPTCGE BIT15
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#define R_PCH_PCR_FIA_PLLCTL 0x20
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#define R_PCH_PCR_FIA_DRCRM1 0x100
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#define R_PCH_PCR_FIA_DRCRM2 0x104
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#define R_PCH_PCR_FIA_DRCRM3 0x108
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#define R_PCH_PCR_FIA_DRCRM4 0x10C // KBL-H only
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#define N_PCH_PCR_FIA_DRCRM_GBEPCKRQM 23
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#define S_PCH_PCR_FIA_DRCRM_BITS_PER_FIELD 4 // CLKREQ number is encoded in 4 bits
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#define S_PCH_PCR_FIA_DRCRM_FIELDS_PER_REG 8 // each DRCRM register contains bitfields for 8 rootports
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#define V_PCH_PCR_FIA_DRCRM_NO_CLKREQ 0 // ClkReq not present
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#define S_PCH_PCR_FIA_DRCRM 4
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#define R_PCH_PCR_FIA_STRPFUSECFG1_REG_BASE 0x200
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#define B_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIE_PEN BIT31
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#define B_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIEPORTSEL (BIT30 | BIT29 | BIT28)
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#define N_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIEPORTSEL 28
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#define R_PCH_PCR_FIA_PCIESATA_FUSECFG_REG_BASE 0x204
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#define R_PCH_PCR_FIA_PCIESATA_STRPCFG_REG_BASE 0x208
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#define R_PCH_PCR_FIA_PCIEUSB3_STRPFUSECFG_REG_BASE 0x20C
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#define R_PCH_PCR_FIA_EXP_FUSECFG_REG_BASE 0x210
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#define R_PCH_PCR_FIA_USB3SSIC_STRPFUSECFG_REG_BASE 0x214
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#define R_PCH_PCR_FIA_CSI3_STRPFUSECFG_REG_BASE 0x218
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#define R_PCH_PCR_FIA_USB3SATA_STRPFUSECFG_REG_BASE 0x21C
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#define R_PCH_PCR_FIA_UFS_STRPFUSECFG_REG_BASE 0x220
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#define R_PCH_PCR_FIA_LOS1_REG_BASE 0x250
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#define R_PCH_PCR_FIA_LOS2_REG_BASE 0x254
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#define R_PCH_PCR_FIA_LOS3_REG_BASE 0x258
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#define R_PCH_PCR_FIA_LOS4_REG_BASE 0x25C
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#define V_PCH_PCR_FIA_LANE_OWN_PCIEDMI 0x0
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#define V_PCH_PCR_FIA_LANE_OWN_USB3 0x1
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#define V_PCH_PCR_FIA_LANE_OWN_SATA 0x2
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#define V_PCH_PCR_FIA_LANE_OWN_GBE 0x3
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#define V_PCH_PCR_FIA_LANE_OWN_MOBEXP 0x4
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#define V_PCH_PCR_FIA_LANE_OWN_SSIC 0x5
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#define V_PCH_PCR_FIA_LANE_OWN_CSI3 0x6
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#define V_PCH_PCR_FIA_LANE_OWN_UFS 0x7
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#define B_PCH_PCR_FIA_L0O (BIT3 | BIT2 | BIT1 | BIT0)
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#define B_PCH_PCR_FIA_L1O (BIT7 | BIT6 | BIT5 | BIT4)
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#define B_PCH_PCR_FIA_L2O (BIT11 | BIT10 | BIT9 | BIT8)
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#define B_PCH_PCR_FIA_L3O (BIT15 | BIT14 | BIT13 | BIT12)
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#define B_PCH_PCR_FIA_L4O (BIT19 | BIT18 | BIT17 | BIT16)
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#define B_PCH_PCR_FIA_L5O (BIT23 | BIT22 | BIT21 | BIT20)
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#define B_PCH_PCR_FIA_L6O (BIT27 | BIT26 | BIT25 | BIT24)
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#define B_PCH_PCR_FIA_L7O (BIT31 | BIT30 | BIT29 | BIT28)
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#define B_PCH_PCR_FIA_L8O (BIT3 | BIT2 | BIT1 | BIT0)
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#define B_PCH_PCR_FIA_L9O (BIT7 | BIT6 | BIT5 | BIT4)
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#define B_PCH_PCR_FIA_L10O (BIT11 | BIT10 | BIT9 | BIT8)
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#define B_PCH_PCR_FIA_L11O (BIT15 | BIT14 | BIT13 | BIT12)
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#define B_PCH_PCR_FIA_L12O (BIT19 | BIT18 | BIT17 | BIT16)
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#define B_PCH_PCR_FIA_L13O (BIT23 | BIT22 | BIT21 | BIT20)
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#define B_PCH_PCR_FIA_L14O (BIT27 | BIT26 | BIT25 | BIT24)
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#define B_PCH_PCR_FIA_L15O (BIT31 | BIT30 | BIT29 | BIT28)
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#define B_PCH_PCR_FIA_L16O (BIT3 | BIT2 | BIT1 | BIT0)
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#define B_PCH_PCR_FIA_L17O (BIT7 | BIT6 | BIT5 | BIT4)
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#define B_PCH_PCR_FIA_L18O (BIT11 | BIT10 | BIT9 | BIT8)
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#define B_PCH_PCR_FIA_L19O (BIT15 | BIT14 | BIT13 | BIT12)
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#define B_PCH_PCR_FIA_L20O (BIT19 | BIT18 | BIT17 | BIT16)
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#define B_PCH_PCR_FIA_L21O (BIT23 | BIT22 | BIT21 | BIT20)
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#define B_PCH_PCR_FIA_L22O (BIT27 | BIT26 | BIT25 | BIT24)
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#define B_PCH_PCR_FIA_L23O (BIT31 | BIT30 | BIT29 | BIT28)
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#define B_PCH_PCR_FIA_L24O (BIT3 | BIT2 | BIT1 | BIT0)
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#define B_PCH_PCR_FIA_L25O (BIT7 | BIT6 | BIT5 | BIT4)
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#define B_PCH_PCR_FIA_L26O (BIT11 | BIT10 | BIT9 | BIT8)
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#define B_PCH_PCR_FIA_L27O (BIT15 | BIT14 | BIT13 | BIT12)
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#define B_PCH_PCR_FIA_L28O (BIT19 | BIT18 | BIT17 | BIT16)
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#define B_PCH_PCR_FIA_L29O (BIT23 | BIT22 | BIT21 | BIT20)
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#define PCH_H_FIA_DMILANE_START 14
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#define PCH_H_FIA_DMILANE_END 17
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#define PCH_FIA_MAX_LANES 34
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#endif
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