/** @file
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Register names for Camera block
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Conventions:
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- Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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- In general, PCH registers are denoted by "_PCH_" in register names
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- Registers / bits that are different between PCH generations are denoted by
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"_PCH_[generation_name]_" in register/bit names.
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- Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
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Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
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e.g., "_PCH_H_", "_PCH_LP_"
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Registers / bits names without _H_ or _LP_ apply for both H and LP.
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- Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
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at the end of the register/bit names
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- Registers / bits of new devices introduced in a PCH generation will be just named
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as "_PCH_" without [generation_name] inserted.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_CAM_H_
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#define _PCH_REGS_CAM_H_
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//
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// CIO2 Registers (D20:F3)
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//
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#define PCI_DEVICE_NUMBER_PCH_CIO2 20
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#define PCI_FUNCTION_NUMBER_PCH_CIO2 3
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#define V_PCH_CIO2_VENDOR_ID V_PCH_INTEL_VENDOR_ID
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#define V_PCH_LP_CIO2_DEVICE_ID 0x9D32
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//
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// CIO2 PCI Configuration space definitions
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//
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#define R_PCH_CIO2_CIOLBA 0x10 // Camera IO Controller Lower Base Address
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#define R_PCH_CIO2_CIOUBA 0x14 // Camera IO Controller Upper Base Address
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#define B_PCH_CIO2_CFG_PMCSR_NSR BIT3 // No Software Reset
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#define R_PCH_CIO2_CFG_MID_MMC 0x90 // MSI Capability ID
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#define R_PCH_CIO2_CFG_MMLA 0x94 // MSI Message Lower Address
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#define R_PCH_CIO2_CFG_MMUA 0x98 // MSI Message Lower Address
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#define R_PCH_CIO2_CFG_MMD 0x9C // MSI Message Data
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#define R_PCH_CIO2_AFID 0xA0 // Advanced Features Capability Identifiers
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#define R_PCH_CIO2_AF_CMD_STS 0xA4 // Adavanced Features Command and Staus Register
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#define R_PCH_CIO2_CFG_PID_PC 0xD0 // Power Management Capability Identifiers
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#define R_PCH_CIO2_CFG_PMCSR 0xD4 // Power Management Control & Status
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#define V_PCH_CIO2_CFG_PMCSR_PS_D3HOT (BIT0 | BIT1)
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//
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// CAM_MMIO_CSI2
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//
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//
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// CAM_MMIO_PRI
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// Camera Pipe Host Controller's MMIO registers in Primary clock domain
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//
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#define R_PCH_CAM_MMIO_PRI_CIO2_CGC 0x1400 ///< CIO2 Clock Gating Control
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#define V_PCH_CAM_MMIO_PRI_CIO2_CGC_CLK_GATING_EN (0x00003D7E)
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#define V_PCH_CAM_MMIO_PRI_CIO2_CGC_CLK_GATING_DIS (0x05300000)
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#define R_PCH_CAM_MMIO_PRI_CIO2_D0I3C 0x1408 ///< CIO2 D0i3 Control Register
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#define B_PCH_CAM_MMIO_PRI_CIO2_D0I3C_I3 BIT2 ///< I3 (D0i3). SW sets this bit to 1 to move the IP into the D0i3 state. Writing this bit to 0 will return the IP to the fully active D0 state (D0i0)
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#define R_PCH_CAM_MMIO_PRI_PCE 0x1430 ///< PCE Power Control Enable Register
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#define B_PCH_CAM_MMIO_PRI_PCE_D3HE BIT2 ///< D3HE: D3-Hot Enable
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#define B_PCH_CAM_MMIO_PRI_PCE_I3E BIT1 ///< I3E: I3 Enable
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#define R_PCH_CAM_MMIO_PRI_CIO2_GPR0 0x1434 ///< CIO2 General Purpose register 0
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#define R_PCH_CAM_MMIO_PRI_CIO2_GPR1 0x1438 ///< CIO2 General Purpose register 1
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//
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// CAM_PVT CHC space defininitions
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// Private registers description for Camera Pipe Host Controller IP
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// MSG IOSF-SB Port 0xA1 (PID_CAM_CHC)
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//
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#define R_PCH_PCR_CAM_CHC_PVT_FUSVAL 0x00 ///< Fuse Value
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#define R_PCH_PCR_CAM_CHC_PVT_ECCLOG 0x04 ///< SRAM Error Count Log
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#define R_PCH_PCR_CAM_CHC_PVT_DBGCTL 0x08 ///< Debug Control
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#define R_PCH_PCR_CAM_CHC_PVT_FNCFG 0x0C ///< Lock bits
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#define B_PCH_PCR_CAM_CHC_PVT_FNCFG_MEM_LOCK BIT8 ///< lock all lockable field in MEM space
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#define B_PCH_PCR_CAM_CHC_PVT_FNCFG_BCLD BIT0 ///< lock all lockable fields in CFG space
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#define R_PCH_PCR_CAM_CHC_HDEVC 0x10 ///< Hidden Device register
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#define R_PCH_PCR_CAM_CHC_PVT_FUSE_DBG 0x14 ///< Hidden Device register
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//
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// fls space definitions
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// CSI2 host controller's FLIS registers
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// MSG IOSF-SB Port 0xAA (PID_CAM_FLS)
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//
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#define R_PCH_PCR_CAM_FLIS_CSI0_RXCNTRL 0x00
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#define R_PCH_PCR_CAM_FLIS_CSI0_RCCRCOMP 0x01
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#define R_PCH_PCR_CAM_FLIS_CSI0_BSCOMPARE 0x02
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#define R_PCH_PCR_CAM_FLIS_CSI1_RXCNTRL 0x03
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#define R_PCH_PCR_CAM_FLIS_CSI1_RCCRCOMP 0x04
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#define R_PCH_PCR_CAM_FLIS_CSI0_INTLPBK_CFG1 0x05
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#define R_PCH_PCR_CAM_FLIS_CSI1_BSCOMPARE 0x06
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#define R_PCH_PCR_CAM_FLIS_CSI0_INTLPBK_CFG2 0x07
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#define R_PCH_PCR_CAM_FLIS_CSI0_INTLPBK_CFG3 0x08
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#define R_PCH_PCR_CAM_FLIS_CSI2_INTLPBK_CFG2 0x09
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#define R_PCH_PCR_CAM_FLIS_CSI2_RXCNTRL 0x0A
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#define R_PCH_PCR_CAM_FLIS_CSI2_RCCRCOMP 0x0B
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#define R_PCH_PCR_CAM_FLIS_CSI2_BSCOMPARE 0x0C
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#define R_PCH_PCR_CAM_FLIS_CSI0_INTLPBK_CMP_STAT 0x0D
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#define R_PCH_PCR_CAM_FLIS_CSI0_INTLPBK_ERR_REG 0x0E
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#define R_PCH_PCR_CAM_FLIS_CSI_CLKTRIM 0x0F
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#define R_PCH_PCR_CAM_FLIS_CSI3_RXCNTRL 0x10
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#define R_PCH_PCR_CAM_FLIS_CSI3_RCCRCOMP 0x11
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#define R_PCH_PCR_CAM_FLIS_CSI3_BSCOMPARE 0x12
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#define R_PCH_PCR_CAM_FLIS_CSI_CFG 0x13
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#define B_PCH_PCR_CAM_FLIS_CSI_CFG_ACIO_LB_EN BIT26
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#define R_PCH_PCR_CAM_FLIS_CSI1_INTLPBK_CFG1 0x14
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#define R_PCH_PCR_CAM_FLIS_CSI1_INTLPBK_CFG2 0x15
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#define R_PCH_PCR_CAM_FLIS_CSI1_INTLPBK_CFG3 0x16
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#define R_PCH_PCR_CAM_FLIS_CSI2_INTLPBK_CFG1 0x17
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#define R_PCH_PCR_CAM_FLIS_CSI2_INTLPBK_CFG3 0x18
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#define R_PCH_PCR_CAM_FLIS_CSI3_INTLPBK_CFG1 0x19
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#define R_PCH_PCR_CAM_FLIS_CSI3_INTLPBK_CFG3 0x1A
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#define R_PCH_PCR_CAM_FLIS_CSI1_INTLPBK_ERR_REG 0x1B
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#define R_PCH_PCR_CAM_FLIS_CSI1_INTLPBK_CMP_STAT 0x1C
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#define R_PCH_PCR_CAM_FLIS_CSI2_INTLPBK_ERR_REG 0x1D
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#define R_PCH_PCR_CAM_FLIS_CSI2_INTLPBK_CMP_STAT 0x1E
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#define R_PCH_PCR_CAM_FLIS_CSI3_INTLPBK_ERR_REG 0x1F
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#define R_PCH_PCR_CAM_FLIS_CSI3_INTLPBK_CMP_STAT 0x20
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#define R_PCH_PCR_CAM_FLIS_CSI_RCOMPSTAT_REG 0x21
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#define R_PCH_PCR_CAM_FLIS_CSI_DLLCTL_REG 0x22
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#define R_PCH_PCR_CAM_FLIS_CSI_DATAEYE_REG 0x23
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#define R_PCH_PCR_CAM_FLIS_CSI_DATATRIM 0x24
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#define R_PCH_PCR_CAM_FLIS_CSI_CTLE 0x25
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#define R_PCH_PCR_CAM_FLIS_CSI0_DFT_CFG 0x26
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#define R_PCH_PCR_CAM_FLIS_CSI1_DFT_CFG 0x27
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#define R_PCH_PCR_CAM_FLIS_CSI2_DFT_CFG 0x28
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#define R_PCH_PCR_CAM_FLIS_CSI3_DFT_CFG 0x29
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#define R_PCH_PCR_CAM_FLIS_CSI_AFE_HS_CONTROL 0x2A
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#define R_PCH_PCR_CAM_FLIS_CSI_RCOMP_STATUS 0x2B
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#define R_PCH_PCR_CAM_FLIS_CSI_RCOMP_CONTROL 0x2C
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#define R_PCH_PCR_CAM_FLIS_CSI_DATAEYE1_REG 0x2D
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#define R_PCH_PCR_CAM_FLIS_CSI_ALL01 0x2E
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#define R_PCH_PCR_CAM_FLIS_CSI_DLLCTL1_REG 0x2F
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#define R_PCH_PCR_CAM_FLIS_CSI_DATATRIM1 0x30
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#endif
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