/** @file
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Definitions required to create PcieStorageInfoHob
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_PCIE_STORAGE_DETECT_HOB_
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#define _PCH_PCIE_STORAGE_DETECT_HOB_
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#include "PchLimits.h"
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#define PCIE_STORAGE_INFO_HOB_REVISION 1
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extern EFI_GUID gPchPcieStorageDetectHobGuid;
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typedef enum {
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RstLinkWidthX1 = 1,
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RstLinkWidthX2 = 2,
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RstLinkWidthX4 = 4
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} RST_LINK_WIDTH;
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//
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// Stores information about connected PCIe storage devices used later by BIOS setup and RST remapping
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//
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#pragma pack(1)
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typedef struct {
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UINT8 Revision;
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//
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// Stores the number of root ports occupied by a connected storage device, values from RST_LINK_WIDTH are supported
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//
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UINT8 PcieStorageLinkWidth[PCH_MAX_PCIE_ROOT_PORTS];
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//
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// Programming interface value for a given device, 0x02 - NVMe or RAID, 0x1 - AHCI storage, 0x0 - no device connected
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//
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UINT8 PcieStorageProgrammingInterface[PCH_MAX_PCIE_ROOT_PORTS];
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//
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// Stores information about cycle router number under a given PCIe controller
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//
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UINT8 RstCycleRouterMap[PCH_MAX_PCIE_CONTROLLERS];
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} PCIE_STORAGE_INFO_HOB;
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#pragma pack()
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#endif
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