/** @file
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Smbus policy
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _SMBUS_CONFIG_H_
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#define _SMBUS_CONFIG_H_
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#define SMBUS_PREMEM_CONFIG_REVISION 1
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extern EFI_GUID gSmbusPreMemConfigGuid;
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#pragma pack (push,1)
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#define PCH_MAX_SMBUS_RESERVED_ADDRESS 128
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///
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/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform.
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///
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typedef struct {
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/**
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Revision 1: Init version
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**/
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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This member describes whether or not the SMBus controller of PCH should be enabled.
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0: Disable; <b>1: Enable</b>.
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**/
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UINT32 Enable : 1;
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UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, <b>0: Disable</b>; 1: Enable.
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UINT32 DynamicPowerGating : 1; ///< <b>(Test)</b> <b>Disable</b> or Enable Smbus dynamic power gating.
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///
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/// <b>(Test)</b> SPD Write Disable, 0: leave SPD Write Disable bit; <b>1: set SPD Write Disable bit.</b>
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/// For security recommendations, SPD write disable bit must be set.
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///
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UINT32 SpdWriteDisable : 1;
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UINT32 RsvdBits0 : 28; ///< Reserved bits
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UINT16 SmbusIoBase; ///< SMBUS Base Address (IO space). Default is <b>0xEFA0</b>.
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UINT8 Rsvd0; ///< Reserved bytes
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UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the RsvdSmbusAddressTable.
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/**
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Array of addresses reserved for non-ARP-capable SMBus devices.
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**/
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UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS];
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} PCH_SMBUS_PREMEM_CONFIG;
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#pragma pack (pop)
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#endif // _SMBUS_CONFIG_H_
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