/** @file
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Serial IO policy
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _SERIAL_IO_CONFIG_H_
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#define _SERIAL_IO_CONFIG_H_
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#define SERIAL_IO_CONFIG_REVISION 1
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extern EFI_GUID gSerialIoConfigGuid;
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#pragma pack (push,1)
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/**
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The PCH_SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers
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to Acpi devices or Pci controllers, and also set the interrupt type to Acpi or Pci
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through Policy. It also provides to configure the I2c0 and I2c1 voltage
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to 1.8v or 3.3v by platform setting.
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Please refer to PeiDxeSmmPchSerialIoLib.h for definition of device numbers and enum values for the below fields
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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0: Disabled; 1: ACPI Mode; <b>2: PCI Mode</b>; 3: Hidden mode, 4: Legacy UART mode, 5: Skip Init
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@note: Considering the PcdSerialIoUartDebugEnable and PcdSerialIoUartNumber for all SerialIo UARTx,
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the PCD is more meaningful to represent the board design. It means, if PcdSerialIoUartDebugEnable is not 0,
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the board is designed to use the SerialIo UART for debug message and the PcdSerialIoUartNumber is dedicated
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to be Debug UART usage. Therefore, it should grayout the option from setup menu since no other options
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available for this UART controller on this board, and also override the policy default accordingly.
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While PcdSerialIoUartDebugEnable is 0, then it's allowed to configure the UART controller by policy.
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@note: While DevMode is set to 5 (Skip Init), BIOS will not initialize this controller. GPIO and PSF configuration is skipped.
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Platform is resonsible for configuring this controller. If platform initializes the Serial IO controller in
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Hidden Mode, it MUST follow the predefined BAR address for the controller.
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**/
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UINT8 DevMode[PCH_SERIALIO_MAX_CONTROLLERS];
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UINT8 Gpio; ///< 0: Disabled; <b>1: Enabled</b>.
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UINT8 I2cVoltage[PCH_SERIALIO_MAX_I2C_CONTROLLERS]; ///< Selects the IO voltage for I2C controllers. It can be 1.8v or 3.3v. <b>0: PchSerialIoIs33V</b>; 1: PchSerialIoIs18V.
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UINT8 SpiCsPolarity[PCH_SERIALIO_MAX_SPI_CONTROLLERS]; ///< Selects SPI ChipSelect signal polarity, <b>0=active low</b>.
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UINT8 UartHwFlowCtrl[PCH_SERIALIO_MAX_UART_CONTROLLERS]; ///< Enables UART hardware flow control, CTS and RTS lines, <b>0:disabled</b>, 1:enabled
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UINT8 Rsvd0[1]; ///< Bytes reserved for reuse when new fields are added to struct
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UINT32 DebugUartNumber : 2; ///< UART number for debug purpose. 0:UART0, 1: UART1, <b>2:UART2</b>
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UINT32 EnableDebugUartAfterPost : 1; ///< Enable debug UART controller after post. 0: diabled, <b>1: enabled</b>
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UINT32 RsvdBits0 : 29;
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} PCH_SERIAL_IO_CONFIG;
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#pragma pack (pop)
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#endif // _SERIAL_IO_CONFIG_H_
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