/** @file
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Sata policy
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _SATA_CONFIG_H_
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#define _SATA_CONFIG_H_
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#define SATA_CONFIG_REVISION 4
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extern EFI_GUID gSataConfigGuid;
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#pragma pack (push,1)
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typedef enum {
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PchSataModeAhci,
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PchSataModeRaid,
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PchSataModeMax
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} PCH_SATA_MODE;
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enum {
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PchSataOromDelay2sec,
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PchSataOromDelay4sec,
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PchSataOromDelay6sec,
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PchSataOromDelay8sec
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} PCH_SATA_OROM_DELAY;
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typedef enum {
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PchSataSpeedDefault,
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PchSataSpeedGen1,
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PchSataSpeedGen2,
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PchSataSpeedGen3
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} PCH_SATA_SPEED;
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/**
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This structure configures the features, property, and capability for each SATA port.
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**/
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typedef struct {
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/**
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Enable SATA port.
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It is highly recommended to disable unused ports for power savings
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**/
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UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>
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UINT32 HotPlug : 1; ///< <b>0: Disable</b>; 1: Enable
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UINT32 InterlockSw : 1; ///< <b>0: Disable</b>; 1: Enable
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UINT32 External : 1; ///< <b>0: Disable</b>; 1: Enable
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UINT32 SpinUp : 1; ///< <b>0: Disable</b>; 1: Enable the COMRESET initialization Sequence to the device
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UINT32 SolidStateDrive : 1; ///< <b>0: HDD</b>; 1: SSD
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UINT32 DevSlp : 1; ///< <b>0: Disable</b>; 1: Enable DEVSLP on the port
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UINT32 EnableDitoConfig : 1; ///< <b>0: Disable</b>; 1: Enable DEVSLP Idle Timeout settings (DmVal, DitoVal)
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UINT32 DmVal : 4; ///< DITO multiplier. Default is <b>15</b>.
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UINT32 DitoVal : 10; ///< DEVSLP Idle Timeout (DITO), Default is <b>625</b>.
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/**
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Support zero power ODD <b>0: Disable</b>, 1: Enable.
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This is also used to disable ModPHY dynamic power gate.
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**/
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UINT32 ZpOdd : 1;
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UINT32 RsvdBits0 : 9; ///< Reserved fields for future expansion w/o protocol change
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} PCH_SATA_PORT_CONFIG;
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/**
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Rapid Storage Technology settings.
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**/
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typedef struct {
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UINT32 RaidAlternateId : 1; ///< @deprecated
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UINT32 Raid0 : 1; ///< 0: Disable; <b>1: Enable</b> RAID0
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UINT32 Raid1 : 1; ///< 0: Disable; <b>1: Enable</b> RAID1
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UINT32 Raid10 : 1; ///< 0: Disable; <b>1: Enable</b> RAID10
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UINT32 Raid5 : 1; ///< 0: Disable; <b>1: Enable</b> RAID5
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UINT32 Irrt : 1; ///< 0: Disable; <b>1: Enable</b> Intel Rapid Recovery Technology
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UINT32 OromUiBanner : 1; ///< 0: Disable; <b>1: Enable</b> OROM UI and BANNER
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UINT32 OromUiDelay : 2; ///< <b>00b: 2 secs</b>; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY)
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UINT32 HddUnlock : 1; ///< 0: Disable; <b>1: Enable</b>. Indicates that the HDD password unlock in the OS is enabled
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UINT32 LedLocate : 1; ///< 0: Disable; <b>1: Enable</b>. Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS
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UINT32 IrrtOnly : 1; ///< 0: Disable; <b>1: Enable</b>. Allow only IRRT drives to span internal and external ports
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UINT32 SmartStorage : 1; ///< 0: Disable; <b>1: Enable</b> RST Smart Storage caching Bit
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UINT32 LegacyOrom : 1; ///< <b>0: Disable</b>; 1: Enable RST Legacy OROM
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/**
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This option allows to configure SATA controller device ID while in RAID mode
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Choosing Client will allow RST driver loading, RSTe driver will not be able to load
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Choosing Alternate will not allow RST inbox driver loading in Windows
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Choosing Server will allow RSTe driver loading, RST driver will not load
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<b>0: Client</b>; 1: Alternate; 2: Server
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**/
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UINT32 RaidDeviceId : 2;
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UINT32 OptaneMemory : 1; ///< 0: Disable; <b>1: Enable</b> RST Optane(TM) Memory
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UINT32 RsvdBits0 : 15; ///< Reserved Bits
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} PCH_SATA_RST_CONFIG;
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/**
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This structure describes the details of Intel RST for PCIe Storage remapping
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Note: In order to use this feature, Intel RST Driver is required
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**/
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typedef struct {
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/**
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This member describes whether or not the Intel RST for PCIe Storage remapping should be enabled. <b>0: Disable</b>; 1: Enable.
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Note 1: If Sata Controller is disabled, PCIe Storage Remapping should be disabled as well
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Note 2: If PCIe Storage remapping is enabled, the PCH integrated AHCI controllers Class Code is configured as RAID
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**/
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UINT32 Enable : 1;
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/**
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Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, <b>0 = autodetect</b>)
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The supported ports for PCIe Storage remapping is different depend on the platform and cycle router, the assignments are as below:
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SKL PCH-LP RST PCIe Storage Cycle Router Assignment:
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i.) RST PCIe Storage Cycle Router 2 -> RP5 - RP8
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ii.) RST PCIe Storage Cycle Router 3 -> RP9 - RP12
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SKL PCH-H RST PCIe Storage Cycle Router Assignment:
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i.) RST PCIe Storage Cycle Router 1 -> RP9 - RP12
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ii.) RST PCIe Storage Cycle Router 2 -> RP13 - RP16
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iii.) RST PCIe Storage Cycle Router 3 -> RP17 - RP20
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**/
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UINT32 RstPcieStoragePort : 5;
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UINT32 RsvdBits0 : 2; ///< Reserved bit
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/**
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PCIe Storage Device Reset Delay in milliseconds (ms), which it guarantees such delay gap is fulfilled
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before PCIe Storage Device configuration space is accessed after an reset caused by the link disable and enable step.
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Default value is <b>100ms</b>.
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**/
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UINT32 DeviceResetDelay : 8;
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UINT32 RsvdBits1 : 16; ///< Reserved bits
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UINT32 Rsvd0[2]; ///< Reserved bytes
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} PCH_RST_PCIE_STORAGE_CONFIG;
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/**
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The PCH_SATA_CONFIG block describes the expected configuration of the SATA controllers.
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>:
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- Added LegacyOrom in RST_SATA_RST_CONFIG to force RST Legacy Orom useage
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<b>Revision 3</b>
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- Added RaidDeviceId in PCH_SATA_RST_CONFIG to allow choice of RAID device id
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<b>Revision 4</b>
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- Added OptaneMemory in PCH_SATA_RST_CONFIG to enable RST optane memory
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**/
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typedef struct {
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/**
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This member specifies the revision of the SATA Configuration structure.
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Any backwards compatible changes to this structure will result in an update in the revision number.
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**/
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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///
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/// This member describes whether or not the SATA controllers should be enabled. 0: Disable; <b>1: Enable</b>.
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///
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UINT32 Enable : 1;
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UINT32 TestMode : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Allow entrance to the PCH SATA test modes
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UINT32 SalpSupport : 1; ///< 0: Disable; <b>1: Enable</b> Aggressive Link Power Management
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UINT32 PwrOptEnable : 1; ///< 0: Disable; <b>1: Enable</b> SATA Power Optimizer on PCH side.
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/**
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EsataSpeedLimit
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When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
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Please be noted, this setting could be cleared by HBA reset, which might be issued
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by EFI AHCI driver when POST time, or by SATA inbox driver/RST driver after POST.
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To support the Speed Limitation when POST, the EFI AHCI driver should preserve the
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setting before and after initialization. For support it after POST, it's dependent on
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driver's behavior.
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<b>0: Disable</b>; 1: Enable
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**/
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UINT32 EsataSpeedLimit : 1;
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UINT32 RsvdBits0 : 27; ///< Reserved bits
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/**
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Determines the system will be configured to which SATA mode (PCH_SATA_MODE). Default is <b>PchSataModeAhci</b>.
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**/
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PCH_SATA_MODE SataMode;
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/**
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Indicates the maximum speed the SATA controller can support
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<b>0h: PchSataSpeedDefault</b>; 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2); 3h: 6 Gb/s (Gen 1)
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**/
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PCH_SATA_SPEED SpeedLimit;
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/**
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This member configures the features, property, and capability for each SATA port.
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**/
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PCH_SATA_PORT_CONFIG PortSettings[PCH_MAX_SATA_PORTS];
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PCH_SATA_RST_CONFIG Rst; ///< Setting applicable to Rapid Storage Technology
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/**
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This member describes the details of implementation of Intel RST for PCIe Storage remapping (Intel RST Driver is required)
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**/
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PCH_RST_PCIE_STORAGE_CONFIG RstPcieStorageRemap[PCH_MAX_RST_PCIE_STORAGE_CR];
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} PCH_SATA_CONFIG;
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#pragma pack (pop)
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#endif // _SATA_CONFIG_H_
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