/** @file
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Power Management policy
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PM_CONFIG_H_
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#define _PM_CONFIG_H_
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#define PM_CONFIG_REVISION 4
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extern EFI_GUID gPmConfigGuid;
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#pragma pack (push,1)
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/**
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This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL, LAN, PCIE wake events.
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**/
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typedef struct {
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/**
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Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register.
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When set to 1, this bit blocks wake events from PME_B0_STS in S5, regardless of the state of PME_B0_EN.
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When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. <b>0: Disable</b>; 1: Enable.
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**/
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UINT32 PmeB0S5Dis : 1;
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UINT32 WolEnableOverride : 1; ///< Corresponds to the "WOL Enable Override" bit in the General PM Configuration B (GEN_PMCON_B) register. 0: Disable; <b>1: Enable</b>.
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UINT32 PcieWakeFromDeepSx : 1; ///< Determine if enable PCIe to wake from deep Sx. <b>0: Disable</b>; 1: Enable.
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UINT32 WoWlanEnable : 1; ///< Determine if WLAN wake from Sx, corresponds to the "HOST_WLAN_PP_EN" bit in the PWRM_CFG3 register. <b>0: Disable</b>; 1: Enable.
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UINT32 WoWlanDeepSxEnable : 1; ///< Determine if WLAN wake from DeepSx, corresponds to the "DSX_WLAN_PP_EN" bit in the PWRM_CFG3 register. <b>0: Disable</b>; 1: Enable.
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UINT32 LanWakeFromDeepSx : 1; ///< Determine if enable LAN to wake from deep Sx. 0: Disable; <b>1: Enable</b>.
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UINT32 RsvdBits0 : 26;
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} PCH_WAKE_CONFIG;
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typedef enum {
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PchDeepSxPolDisable,
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PchDpS5BatteryEn,
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PchDpS5AlwaysEn,
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PchDpS4S5BatteryEn,
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PchDpS4S5AlwaysEn,
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PchDpS3S4S5BatteryEn,
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PchDpS3S4S5AlwaysEn
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} PCH_DEEP_SX_CONFIG;
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typedef enum {
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PchSlpS360us,
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PchSlpS31ms,
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PchSlpS350ms,
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PchSlpS32s
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} PCH_SLP_S3_MIN_ASSERT;
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typedef enum {
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PchSlpS4PchTime, ///< The time defined in PCH EDS Power Sequencing and Reset Signal Timings table
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PchSlpS41s,
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PchSlpS42s,
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PchSlpS43s,
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PchSlpS44s
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} PCH_SLP_S4_MIN_ASSERT;
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typedef enum {
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PchSlpSus0ms,
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PchSlpSus500ms,
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PchSlpSus1s,
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PchSlpSus4s
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} PCH_SLP_SUS_MIN_ASSERT;
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typedef enum {
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PchSlpA0ms,
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PchSlpA4s,
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PchSlpA98ms,
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PchSlpA2s
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} PCH_SLP_A_MIN_ASSERT;
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/**
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The PCH_PM_CONFIG block describes expected miscellaneous power management settings.
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The PowerResetStatusClear field would clear the Power/Reset status bits, please
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set the bits if you want PCH Init driver to clear it, if you want to check the
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status later then clear the bits.
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>:
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- Deprecate CapsuleResetType and the capsule update always uses warmreset cycle.
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<b>Revision 3</b>:
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- Added SlpS0VmEnable.
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<b>Revision 4</b>
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- Deprecate PciePllSsc and moved to PCH_HSIO_PCIE_PREMEM_CONFIG
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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PCH_WAKE_CONFIG WakeConfig; ///< Specify Wake Policy
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UINT32 PchDeepSxPol : 4; ///< Deep Sx Policy. Refer to PCH_DEEP_SX_CONFIG for each value. Default is <b>PchDeepSxPolDisable</b>.
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UINT32 PchSlpS3MinAssert : 4; ///< SLP_S3 Minimum Assertion Width Policy. Refer to PCH_SLP_S3_MIN_ASSERT for each value. Default is <b>PchSlpS350ms</b>.
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UINT32 PchSlpS4MinAssert : 4; ///< SLP_S4 Minimum Assertion Width Policy. Refer to PCH_SLP_S4_MIN_ASSERT for each value. Default is <b>PchSlpS44s</b>.
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UINT32 PchSlpSusMinAssert : 4; ///< SLP_SUS Minimum Assertion Width Policy. Refer to PCH_SLP_SUS_MIN_ASSERT for each value. Default is <b>PchSlpSus4s</b>.
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UINT32 PchSlpAMinAssert : 4; ///< SLP_A Minimum Assertion Width Policy. Refer to PCH_SLP_A_MIN_ASSERT for each value. Default is <b>PchSlpA2s</b>.
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UINT32 RsvdBits0 : 12;
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/**
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This member describes whether or not the LPC ClockRun feature of PCH should
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be enabled. <b>0: Disable</b>; 1: Enable
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**/
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UINT32 LpcClockRun : 1;
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UINT32 SlpStrchSusUp : 1; ///< <b>0: Disable</b>; 1: Enable SLP_X Stretching After SUS Well Power Up
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/**
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Enable/Disable SLP_LAN# Low on DC Power. 0: Disable; <b>1: Enable</b>.
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Configure On DC PHY Power Diable according to policy SlpLanLowDc.
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When this is enabled, SLP_LAN# will be driven low when ACPRESENT is low.
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This indicates that LAN PHY should be powered off on battery mode.
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This will override the DC_PP_DIS setting by WolEnableOverride.
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**/
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UINT32 SlpLanLowDc : 1;
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/**
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PCH power button override period.
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000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s
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<b>Default is 0: 4s</b>
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**/
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UINT32 PwrBtnOverridePeriod : 3;
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/**
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<b>(Test)</b>
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Disable/Enable PCH to CPU enery report feature. <b>0: Disable</b>; 1: Enable.
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Enery Report is must have feature. Wihtout Energy Report, the performance report
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by workloads/benchmarks will be unrealistic because PCH's energy is not being accounted
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in power/performance management algorithm.
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If for some reason PCH energy report is too high, which forces CPU to try to reduce
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its power by throttling, then it could try to disable Energy Report to do first debug.
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This might be due to energy scaling factors are not correct or the LPM settings are not
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kicking in.
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**/
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UINT32 DisableEnergyReport : 1;
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/**
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When set to Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
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When set to Enable, PCH will not pull down AC_PRESENT.
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This setting is ignored when DeepSx is not supported.
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Default is <b>0:Disable</b>
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**/
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UINT32 DisableDsxAcPresentPulldown : 1;
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/**
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<b>(Test)</b>
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When set to true, this bit disallows host reads to PMC XRAM.
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BIOS must set this bit (to disable and lock the feature) prior to passing control to OS
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0:Disable, <b>1:Enable</b>
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**/
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UINT32 PmcReadDisable : 1;
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/**
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@deprecated This determines the type of reset issued during the capsule update process by UpdateCapsule().
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Always Warm reset.
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**/
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UINT32 CapsuleResetType : 1;
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/**
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Power button native mode disable.
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While FALSE, the PMC's power button logic will act upon the input value from the GPIO unit, as normal.
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While TRUE, this will result in the PMC logic constantly seeing the power button as de-asserted.
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<b>Default is FALSE.</b>
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**/
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UINT32 DisableNativePowerButton : 1;
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/**
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Indicates whether SLP_S0# is to be asserted when PCH reaches idle state.
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When set to one SLP_S0# will be asserted in idle state.
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When set to zero SLP_S0# will not toggle and is always drivern high.
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0:Disable, <b>1:Enable</b>
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@warning: In SKL PCH VCCPRIM_CORE must NOT be reduced based on SLP_S0# being asserted.
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If a platform is using SLP_S0 to lower PCH voltage the below policy must be disabled.
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**/
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UINT32 SlpS0Enable : 1;
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UINT32 MeWakeSts : 1; ///< Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; <b>1: Enable</b>.
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UINT32 WolOvrWkSts : 1; ///< Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; <b>1: Enable</b>.
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/**
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Set true to enable TCO timer.
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When FALSE, it disables PCH ACPI timer, and stops TCO timer.
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@note: This will have significant power impact when it's enabled.
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If TCO timer is disabled, uCode ACPI timer emulation must be enabled,
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and WDAT table must not be exposed to the OS.
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<b>0: Disable</b>, 1: Enable
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**/
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UINT32 EnableTcoTimer : 1;
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/**
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Indicates platform has support for VCCPrim_Core Voltage Margining in SLP_S0# asserted state.
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0: Disable, <b>1: Enable</b>
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**/
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UINT32 SlpS0VmEnable : 1;
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UINT32 RsvdBits1 : 16;
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/**
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Reset Power Cycle Duration could be customized in the unit of second. Please refer to EDS
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for all support settings. PCH HW default is 4 seconds, and range is 1~4 seconds, where
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<b>0 is default</b>, 1 is 1 second, 2 is 2 seconds, ... 4 is 4 seconds.
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And make sure the setting correct, which never less than the following register.
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- GEN_PMCON_B.SLP_S3_MIN_ASST_WDTH
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- GEN_PMCON_B.SLP_S4_MIN_ASST_WDTH
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- PWRM_CFG.SLP_A_MIN_ASST_WDTH
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- PWRM_CFG.SLP_LAN_MIN_ASST_WDTH
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**/
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UINT8 PchPwrCycDur;
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/**
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@deprecated since revision 4
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Specifies the Pcie Pll Spread Spectrum Percentage
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The value of this policy is in 1/10th percent units.
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Valid spread range is 0-20. A value of 0xFF is reserved for AUTO.
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A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0%
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The default is <b>0xFF: AUTO - No BIOS override</b>.
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**/
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UINT8 PciePllSsc;
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UINT8 Rsvd0[2]; ///< Reserved bytes
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} PCH_PM_CONFIG;
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#pragma pack (pop)
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#endif // _PM_CONFIG_H_
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