/** @file
|
Pcie root port policy
|
|
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
|
**/
|
#ifndef _PCH_PCIE_CONFIG_H_
|
#define _PCH_PCIE_CONFIG_H_
|
|
#define PCIE_RP_CONFIG_REVISION 4
|
#define PCIE_RP_PREMEM_CONFIG_REVISION 1
|
|
extern EFI_GUID gPcieRpConfigGuid;
|
extern EFI_GUID gPcieRpPreMemConfigGuid;
|
|
#pragma pack (push,1)
|
|
#define PCH_PCIE_SWEQ_COEFFS_MAX 5
|
|
typedef enum {
|
PchPcieOverrideDisabled = 0,
|
PchPcieL1L2Override = 0x01,
|
PchPcieL1SubstatesOverride = 0x02,
|
PchPcieL1L2AndL1SubstatesOverride = 0x03,
|
PchPcieLtrOverride = 0x04
|
} PCH_PCIE_OVERRIDE_CONFIG;
|
|
/**
|
PCIe device table entry entry
|
|
The PCIe device table is being used to override PCIe device ASPM settings.
|
To take effect table consisting of such entries must be instelled as PPI
|
on gPchPcieDeviceTablePpiGuid.
|
Last entry VendorId must be 0.
|
**/
|
typedef struct {
|
UINT16 VendorId; ///< The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID
|
UINT16 DeviceId; ///< The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID
|
UINT8 RevId; ///< The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings
|
UINT8 BaseClassCode; ///< The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class
|
UINT8 SubClassCode; ///< The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class
|
UINT8 EndPointAspm; ///< Override device ASPM (see: PCH_PCIE_ASPM_CONTROL)
|
///< Bit 1 must be set in OverrideConfig for this field to take effect
|
UINT16 OverrideConfig; ///< The override config bitmap (see: PCH_PCIE_OVERRIDE_CONFIG).
|
/**
|
The L1Substates Capability Offset Override. (applicable if bit 2 is set in OverrideConfig)
|
This field can be zero if only the L1 Substate value is going to be override.
|
**/
|
UINT16 L1SubstatesCapOffset;
|
/**
|
L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideConfig)
|
Set to zero then the L1 Substate Capability [3:0] is ignored, and only L1s values are override.
|
Only bit [3:0] are applicable. Other bits are ignored.
|
**/
|
UINT8 L1SubstatesCapMask;
|
/**
|
L1 Substate Port Common Mode Restore Time Override. (applicable if bit 2 is set in OverrideConfig)
|
L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
|
If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
|
and only L1SubstatesCapOffset is override.
|
**/
|
UINT8 L1sCommonModeRestoreTime;
|
/**
|
L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set in OverrideConfig)
|
L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
|
If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
|
and only L1SubstatesCapOffset is override.
|
**/
|
UINT8 L1sTpowerOnScale;
|
/**
|
L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set in OverrideConfig)
|
L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
|
If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
|
and only L1SubstatesCapOffset is override.
|
**/
|
UINT8 L1sTpowerOnValue;
|
|
/**
|
SnoopLatency bit definition
|
Note: All Reserved bits must be set to 0
|
|
BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
|
When clear values in bits 9:0 will be ignored
|
BITS[14:13] - Reserved
|
BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
|
000b - 1 ns
|
001b - 32 ns
|
010b - 1024 ns
|
011b - 32,768 ns
|
100b - 1,048,576 ns
|
101b - 33,554,432 ns
|
110b - Reserved
|
111b - Reserved
|
BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with
|
the scale in bits 12:10
|
|
This field takes effect only if bit 3 is set in OverrideConfig.
|
**/
|
UINT16 SnoopLatency;
|
/**
|
NonSnoopLatency bit definition
|
Note: All Reserved bits must be set to 0
|
|
BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
|
When clear values in bits 9:0 will be ignored
|
BITS[14:13] - Reserved
|
BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
|
000b - 1 ns
|
001b - 32 ns
|
010b - 1024 ns
|
011b - 32,768 ns
|
100b - 1,048,576 ns
|
101b - 33,554,432 ns
|
110b - Reserved
|
111b - Reserved
|
BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with
|
the scale in bits 12:10
|
|
This field takes effect only if bit 3 is set in OverrideConfig.
|
**/
|
UINT16 NonSnoopLatency;
|
|
/**
|
Forces LTR override to be permanent
|
The default way LTR override works is:
|
rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message
|
This settings allows force override of LTR mechanism. If it's enabled, then:
|
rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored
|
**/
|
UINT8 ForceLtrOverride;
|
UINT8 Reserved[3];
|
} PCH_PCIE_DEVICE_OVERRIDE;
|
|
enum PCH_PCIE_SPEED {
|
PchPcieAuto,
|
PchPcieGen1,
|
PchPcieGen2,
|
PchPcieGen3
|
};
|
|
///
|
/// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature
|
///
|
typedef enum {
|
PchPcieAspmDisabled,
|
PchPcieAspmL0s,
|
PchPcieAspmL1,
|
PchPcieAspmL0sL1,
|
PchPcieAspmAutoConfig,
|
PchPcieAspmMax
|
} PCH_PCIE_ASPM_CONTROL;
|
|
/**
|
Refer to PCH EDS for the PCH implementation values corresponding
|
to below PCI-E spec defined ranges
|
**/
|
typedef enum {
|
PchPcieL1SubstatesDisabled,
|
PchPcieL1SubstatesL1_1,
|
PchPcieL1SubstatesL1_2,
|
PchPcieL1SubstatesL1_1_2,
|
PchPcieL1SubstatesMax
|
} PCH_PCIE_L1SUBSTATES_CONTROL;
|
|
enum PCH_PCIE_MAX_PAYLOAD {
|
PchPcieMaxPayload128 = 0,
|
PchPcieMaxPayload256,
|
PchPcieMaxPayloadMax
|
};
|
|
enum PCH_PCIE_COMPLETION_TIMEOUT {
|
PchPcieCompletionTO_Default,
|
PchPcieCompletionTO_50_100us,
|
PchPcieCompletionTO_1_10ms,
|
PchPcieCompletionTO_16_55ms,
|
PchPcieCompletionTO_65_210ms,
|
PchPcieCompletionTO_260_900ms,
|
PchPcieCompletionTO_1_3P5s,
|
PchPcieCompletionTO_4_13s,
|
PchPcieCompletionTO_17_64s,
|
PchPcieCompletionTO_Disabled
|
};
|
|
typedef enum {
|
PchPcieEqDefault = 0, ///< Use reference code default (software margining)
|
PchPcieEqHardware = 1, ///< Hardware equalization (experimental), note this requires PCH-LP C0 or PCH-H D0 or newer
|
PchPcieEqSoftware = 2, ///< Use software margining flow
|
PchPcieEqStaticCoeff = 4 ///< Fixed equalization (requires Coefficient settings per lane)
|
} PCH_PCIE_EQ_METHOD;
|
|
/**
|
Represent lane specific PCIe Gen3 equalization parameters.
|
**/
|
typedef struct {
|
UINT8 Cm; ///< Coefficient C-1
|
UINT8 Cp; ///< Coefficient C+1
|
UINT8 Rsvd0[2]; ///< Reserved bytes
|
} PCH_PCIE_EQ_LANE_PARAM, PCH_PCIE_EQ_PARAM;
|
|
/**
|
The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port.
|
**/
|
typedef struct {
|
UINT32 Enable : 1; ///< @deprecated.
|
UINT32 HotPlug : 1; ///< Indicate whether the root port is hot plug available. <b>0: Disable</b>; 1: Enable.
|
UINT32 PmSci : 1; ///< Indicate whether the root port power manager SCI is enabled. 0: Disable; <b>1: Enable</b>.
|
UINT32 ExtSync : 1; ///< Indicate whether the extended synch is enabled. <b>0: Disable</b>; 1: Enable.
|
UINT32 TransmitterHalfSwing : 1; ///< Indicate whether the Transmitter Half Swing is enabled. <b>0: Disable</b>; 1: Enable.
|
UINT32 AcsEnabled : 1; ///< Indicate whether the ACS is enabled. 0: Disable; <b>1: Enable</b>.
|
UINT32 RsvdBits0 : 5; ///< Reserved bits.
|
UINT32 ClkReqSupported : 1; ///< Indicate whether dedicated CLKREQ# is supported by the port.
|
/**
|
The ClkReq Signal mapped to this root port. Default is zero. Valid if ClkReqSupported is TRUE.
|
This Number should not exceed the Maximum Available ClkReq Signals for LP and H.
|
**/
|
UINT32 ClkReqNumber : 4;
|
/**
|
Probe CLKREQ# signal before enabling CLKREQ# based power management.
|
Conforming device shall hold CLKREQ# low until CPM is enabled. This feature attempts
|
to verify CLKREQ# signal is connected by testing pad state before enabling CPM.
|
In particular this helps to avoid issues with open-ended PCIe slots.
|
This is only applicable to non hot-plug ports.
|
<b>0: Disable</b>; 1: Enable.
|
**/
|
UINT32 ClkReqDetect : 1;
|
//
|
// Error handlings
|
//
|
UINT32 AdvancedErrorReporting : 1; ///< Indicate whether the Advanced Error Reporting is enabled. <b>0: Disable</b>; 1: Enable.
|
UINT32 UnsupportedRequestReport : 1; ///< Indicate whether the Unsupported Request Report is enabled. <b>0: Disable</b>; 1: Enable.
|
UINT32 FatalErrorReport : 1; ///< Indicate whether the Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
|
UINT32 NoFatalErrorReport : 1; ///< Indicate whether the No Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
|
UINT32 CorrectableErrorReport : 1; ///< Indicate whether the Correctable Error Report is enabled. <b>0: Disable</b>; 1: Enable.
|
UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether the System Error on Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
|
UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether the System Error on Non Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
|
UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether the System Error on Correctable Error is enabled. <b>0: Disable</b>; 1: Enable.
|
/**
|
Max Payload Size supported, Default <b>128B</b>, see enum PCH_PCIE_MAX_PAYLOAD
|
Changes Max Payload Size Supported field in Device Capabilities of the root port.
|
**/
|
UINT32 MaxPayload : 2;
|
UINT32 EnableHotplugSmi : 1; ///< Indicate whether the Hotplug Smi for Rootport is enabled, for TBT rootport we need to disable hotplug smi. 0: Disable; <b>1: Enable </b>.
|
UINT32 RsvdBits1 : 3; ///< Reserved fields for future expansion w/o protocol change
|
|
UINT32 DeviceResetPadActiveHigh : 1; ///< Indicated whether PERST# is active <b>0: Low</b>; 1: High, See: DeviceResetPad
|
/**
|
Determines each PCIE Port speed capability.
|
<b>0: Auto</b>; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED)
|
**/
|
UINT8 PcieSpeed;
|
/**
|
PCIe Gen3 Equalization Phase 3 Method (see PCH_PCIE_EQ_METHOD).
|
<b>0: Default</b>; 2: Software Search; 4: Fixed Coefficients
|
**/
|
UINT8 Gen3EqPh3Method;
|
|
UINT8 PhysicalSlotNumber; ///< Indicates the slot number for the root port. Default is the value as root port index.
|
UINT8 CompletionTimeout; ///< The completion timeout configuration of the root port (see: PCH_PCIE_COMPLETION_TIMEOUT). Default is <b>PchPcieCompletionTO_Default</b>.
|
/**
|
The PCH pin assigned to device PERST# signal if available, zero otherwise.
|
This entry is used mainly in Gen3 software equalization flow. It is necessary for some devices
|
(mainly some graphic adapters) to successfully complete the software equalization flow.
|
See also DeviceResetPadActiveHigh
|
**/
|
UINT32 DeviceResetPad;
|
UINT32 Rsvd1; ///< Reserved bytes
|
//
|
// Power Management
|
//
|
UINT8 Aspm; ///< The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is <b>PchPcieAspmAutoConfig</b>.
|
UINT8 L1Substates; ///< The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is <b>PchPcieL1SubstatesL1_1_2</b>.
|
UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism. <b>0: Disable</b>; 1: Enable.
|
UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable.
|
UINT16 LtrMaxSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Snoop Latency.
|
UINT16 LtrMaxNoSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Non-Snoop Latency.
|
UINT8 SnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Mode.
|
UINT8 SnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Multiplier.
|
UINT16 SnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Value.
|
UINT8 NonSnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
|
UINT8 NonSnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
|
UINT16 NonSnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Value.
|
UINT32 SlotPowerLimitScale : 2; ///< <b>(Test)</b> Specifies scale used for slot power limit value. Leave as 0 to set to default. Default is <b>zero</b>.
|
UINT32 SlotPowerLimitValue : 12; ///< <b>(Test)</b> Specifies upper limit on power supplies by slot. Leave as 0 to set to default. Default is <b>zero</b>.
|
//
|
// Gen3 Equalization settings
|
//
|
UINT32 Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>5</b>.
|
UINT32 Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>7</b>.
|
/**
|
Forces LTR override to be permanent
|
The default way LTR override works is:
|
rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message
|
This settings allows force override of LTR mechanism. If it's enabled, then:
|
rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored
|
**/
|
UINT32 ForceLtrOverride : 1;
|
UINT32 EnableCpm : 1; ///< Enables Clock Power Management; even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism
|
UINT32 RsvdBits3 : 8; ///< Reserved Bits
|
/**
|
The number of milliseconds reference code will wait for link to exit Detect state for enabled ports
|
before assuming there is no device and potentially disabling the port.
|
It's assumed that the link will exit detect state before root port initialization (sufficient time
|
elapsed since PLTRST de-assertion) therefore default timeout is zero. However this might be useful
|
if device power-up seqence is controlled by BIOS or a specific device requires more time to detect.
|
In case of non-common clock enabled the default timout is 15ms.
|
<b>Default: 0</b>
|
**/
|
UINT16 DetectTimeoutMs;
|
UINT16 Rsvd2; ///< Reserved bytes
|
UINT32 Rsvd3; ///< Reserved bytes
|
} PCH_PCIE_ROOT_PORT_CONFIG;
|
|
/**
|
The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers
|
<b>Revision 1</b>: Init version
|
<b>Revision 2</b>: Deprecate the PCIE RP enable in post mem.
|
<b>Revision 3</b>: Added DetectTimeoutMs parameter per port. The common DetectTimeoutMs is obsolete.
|
<b>Revision 4</b>: Added EnableHotplugSmi parameter per port.
|
**/
|
typedef struct {
|
CONFIG_BLOCK_HEADER Header; ///< Config Block Header
|
///
|
/// These members describe the configuration of each PCH PCIe root port.
|
///
|
PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS];
|
///
|
/// Gen3 Equalization settings for physical PCIe lane, index 0 represents PCIe lane 1, etc.
|
/// Corresponding entries are used when root port EqPh3Method is PchPcieEqStaticCoeff (default).
|
///
|
PCH_PCIE_EQ_LANE_PARAM EqPh3LaneParam[PCH_MAX_PCIE_ROOT_PORTS];
|
///
|
/// List of coefficients used during equalization (applicable to both software and hardware EQ)
|
///
|
PCH_PCIE_EQ_PARAM SwEqCoeffList[PCH_PCIE_SWEQ_COEFFS_MAX];
|
PCH_PCIE_EQ_PARAM Rsvd0[3];
|
///
|
/// <b>(Test)</b> This member describes whether PCIE root port Port 8xh Decode is enabled. <b>0: Disable</b>; 1: Enable.
|
///
|
UINT32 EnablePort8xhDecode : 1;
|
///
|
/// <b>(Test)</b> The Index of PCIe Port that is selected for Port8xh Decode (0 Based)
|
///
|
UINT32 PchPciePort8xhDecodePortIndex : 5;
|
///
|
/// This member describes whether the PCI Express Clock Gating for each root port
|
/// is enabled by platform modules. <b>0: Disable</b>; 1: Enable.
|
///
|
UINT32 DisableRootPortClockGating : 1;
|
///
|
/// This member describes whether Peer Memory Writes are enabled on the platform. <b>0: Disable</b>; 1: Enable.
|
///
|
UINT32 EnablePeerMemoryWrite : 1;
|
/**
|
This member allows BIOS to control ICC PLL Shutdown by determining PCIe devices are LTR capable
|
or leaving untouched.
|
- <b>0: Disable, ICC PLL Shutdown is determined by PCIe device LTR capablility.</b>
|
- To allow ICC PLL shutdown if all present PCIe devices are LTR capable or if no PCIe devices are
|
presented for maximum power savings where possible.
|
- To disable ICC PLL shutdown when BIOS detects any non-LTR capable PCIe device for ensuring device
|
functionality.
|
- 1: Enable, To allow ICC PLL shutdown even if some devices do not support LTR capability.
|
**/
|
UINT32 AllowNoLtrIccPllShutdown : 1;
|
/**
|
Compliance Test Mode shall be enabled when using Compliance Load Board.
|
<b>0: Disable</b>, 1: Enable
|
**/
|
UINT32 ComplianceTestMode : 1;
|
/**
|
RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is disabled.
|
A PCIE device can have higher functions only when Function0 exists. To satisfy this requirement,
|
BIOS will always enable Function0 of a device that contains more than 0 enabled root ports.
|
- <b>Enabled: One of enabled root ports get assigned to Function0.</b>
|
This offers no guarantee that any particular root port will be available at a specific DevNr:FuncNr location
|
- Disabled: Root port that corresponds to Function0 will be kept visible even though it might be not used.
|
That way rootport - to - DevNr:FuncNr assignment is constant. This option will impact ports 1, 9, 17.
|
NOTE: This option will not work if ports 1, 9, 17 are fused or configured for RST PCIe storage
|
NOTE: Disabling function swap may have adverse impact on power management. This option should ONLY
|
be used when each one of root ports 1, 9, 17:
|
- is configured as PCIe and has correctly configured ClkReq signal, or
|
- does not own any mPhy lanes (they are configured as SATA or USB)
|
**/
|
UINT32 RpFunctionSwap : 1;
|
|
UINT32 RsvdBits0 : 21;
|
/**
|
@deprecated since revision 3, substituted by per-port timeout parameter
|
The number of milliseconds reference code will wait for link to exit Detect state for enabled ports
|
before assuming there is no device and potentially disabling the port.
|
It's assumed that the link will exit detect state before root port initialization (sufficient time
|
elapsed since PLTRST de-assertion) therefore default timeout is zero. However this might be useful
|
if device power-up sequence is controlled by BIOS or a specific device requires more time to detect.
|
I case of non-common clock enabled the default timeout is 15ms.
|
<b>Default: 0</b>
|
**/
|
UINT16 DetectTimeoutMs;
|
UINT16 Rsvd1; ///< Reserved bytes
|
/**
|
PCIe device override table
|
The PCIe device table is being used to override PCIe device ASPM settings.
|
This is a pointer points to a 32bit address. And it's only used in PostMem phase.
|
Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table.
|
Last entry VendorId must be 0.
|
The prototype of this policy is:
|
PCH_PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;
|
**/
|
UINT32 PcieDeviceOverrideTablePtr;
|
|
} PCH_PCIE_CONFIG;
|
|
/**
|
The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers
|
Revision 1: Init version
|
Add RpEnable in premem phase.
|
**/
|
typedef struct {
|
CONFIG_BLOCK_HEADER Header; ///< Config Block Header
|
/**
|
Root Port enabling mask.
|
Bit0 presents RP1, Bit1 presents RP2, and so on.
|
0: Disable; <b>1: Enable</b>.
|
**/
|
UINT32 RpEnabledMask;
|
} PCH_PCIE_RP_PREMEM_CONFIG;
|
|
#pragma pack (pop)
|
|
#endif // _PCH_PCIE_CONFIG_H_
|
