/** @file
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PCH General policy
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_GENERAL_CONFIG_H_
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#define _PCH_GENERAL_CONFIG_H_
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#define PCH_GENERAL_CONFIG_REVISION 1
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#define PCH_GENERAL_PREMEM_CONFIG_REVISION 1
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extern EFI_GUID gPchGeneralConfigGuid;
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extern EFI_GUID gPchGeneralPreMemConfigGuid;
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#pragma pack (push,1)
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enum PCH_RESERVED_PAGE_ROUTE {
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PchReservedPageToLpc, ///< Port 80h cycles are sent to LPC.
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PchReservedPageToPcie ///< Port 80h cycles are sent to PCIe.
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};
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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Subsystem Vendor ID and Subsystem ID of the PCH devices.
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This fields will be ignored if the value of SubSystemVendorId and SubSystemId
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are both 0.
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**/
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UINT16 SubSystemVendorId; ///< Default Subsystem Vendor ID of the PCH devices. Default is <b>0x8086</b>
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UINT16 SubSystemId; ///< Default Subsystem ID of the PCH devices. Default is <b>0x7270</b>
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/**
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This member describes whether or not the Compatibility Revision ID (CRID) feature
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of PCH should be enabled. <b>0: Disable</b>; 1: Enable
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**/
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UINT32 Crid : 1;
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UINT32 RsvdBits0 : 31; ///< Reserved bits
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} PCH_GENERAL_CONFIG;
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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UINT16 AcpiBase; ///< Power management I/O base address. Default is <b>0x1800</b>.
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UINT8 RsvdBytes[2];
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/**
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Control where the Port 80h cycles are sent, <b>0: LPC</b>; 1: PCI.
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**/
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UINT32 Port80Route : 1;
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UINT32 RsvdBits0 : 31; ///< Reserved bits
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} PCH_GENERAL_PREMEM_CONFIG;
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#pragma pack (pop)
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#endif // _PCH_GENERAL_CONFIG_H_
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