/** @file
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Interrupt policy
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _INTERRUPT_CONFIG_H_
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#define _INTERRUPT_CONFIG_H_
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#define INTERRUPT_CONFIG_REVISION 1
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extern EFI_GUID gInterruptConfigGuid;
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#pragma pack (push,1)
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//
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// --------------------- Interrupts Config ------------------------------
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//
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typedef enum {
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PchNoInt, ///< No Interrupt Pin
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PchIntA,
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PchIntB,
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PchIntC,
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PchIntD
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} PCH_INT_PIN;
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///
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/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
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///
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typedef struct {
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UINT8 Device; ///< Device number
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UINT8 Function; ///< Device function
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UINT8 IntX; ///< Interrupt pin: INTA-INTD (see PCH_INT_PIN)
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UINT8 Irq; ///< IRQ to be set for device.
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} PCH_DEVICE_INTERRUPT_CONFIG;
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#define PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
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#define PCH_MAX_PXRC_CONFIG 8 ///< Number of PXRC registers in ITSS
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///
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/// The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH.
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///
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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UINT8 NumOfDevIntConfig; ///< Number of entries in DevIntConfig table
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UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4.
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PCH_DEVICE_INTERRUPT_CONFIG DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFIG]; ///< Array which stores PCH devices interrupts settings
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UINT8 PxRcConfig[PCH_MAX_PXRC_CONFIG]; ///< Array which stores interrupt routing for 8259 controller
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UINT8 GpioIrqRoute; ///< Interrupt routing for GPIO. Default is <b>14</b>.
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UINT8 SciIrqSelect; ///< Interrupt select for SCI. Default is <b>9</b>.
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UINT8 TcoIrqSelect; ///< Interrupt select for TCO. Default is <b>9</b>.
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UINT8 TcoIrqEnable; ///< Enable IRQ generation for TCO. <b>0: Disable</b>; 1: Enable.
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} PCH_INTERRUPT_CONFIG;
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#pragma pack (pop)
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#endif // _INTERRUPT_CONFIG_H_
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