/** @file
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Hsio Sata policy
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _HSIO_SATA_CONFIG_H_
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#define _HSIO_SATA_CONFIG_H_
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#define HSIO_SATA_PREMEM_CONFIG_REVISION 1
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extern EFI_GUID gHsioSataPreMemConfigGuid;
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#pragma pack (push,1)
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/**
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The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port lane
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**/
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typedef struct {
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//
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// HSIO Rx Eq
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//
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UINT32 HsioRxGen1EqBoostMagEnable : 1; ///< <b>0: Disable</b>; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
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UINT32 HsioRxGen1EqBoostMag : 6; ///< SATA 1.5 Gb/sReceiver Equalization Boost Magnitude Adjustment value
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UINT32 HsioRxGen2EqBoostMagEnable : 1; ///< <b>0: Disable</b>; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
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UINT32 HsioRxGen2EqBoostMag : 6; ///< SATA 3.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value
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UINT32 HsioRxGen3EqBoostMagEnable : 1; ///< <b>0: Disable</b>; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
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UINT32 HsioRxGen3EqBoostMag : 6; ///< SATA 6.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value
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//
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// HSIO Tx Eq
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//
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UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
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UINT32 HsioTxGen1DownscaleAmp : 6; ///< SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
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UINT32 RsvdBits0 : 4; ///< Reserved bits
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UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
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UINT32 HsioTxGen2DownscaleAmp : 6; ///< SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment
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UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
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UINT32 HsioTxGen3DownscaleAmp : 6; ///< SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment
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UINT32 HsioTxGen1DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
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UINT32 HsioTxGen1DeEmph : 6; ///< SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
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UINT32 HsioTxGen2DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
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UINT32 HsioTxGen2DeEmph : 6; ///< SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
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UINT32 RsvdBits1 : 4; ///< Reserved bits
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UINT32 HsioTxGen3DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
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UINT32 HsioTxGen3DeEmph : 6; ///< SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
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UINT32 RsvdBits2 : 25; ///< Reserved bits
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} PCH_HSIO_SATA_PORT_LANE;
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///
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/// The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of the SATA controller.
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///
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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///
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/// These members describe the configuration of HSIO for SATA lanes.
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///
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PCH_HSIO_SATA_PORT_LANE PortLane[PCH_MAX_SATA_PORTS];
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} PCH_HSIO_SATA_PREMEM_CONFIG;
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#pragma pack (pop)
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#endif // _HSIO_SATA_CONFIG_H_
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