/** @file
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FlashProtection policy
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _FLASH_PROTECTION_CONFIG_H_
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#define _FLASH_PROTECTION_CONFIG_H_
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#define FLASH_PROTECTION_CONFIG_REVISION 1
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extern EFI_GUID gFlashProtectionConfigGuid;
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#pragma pack (push,1)
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/**
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The PCH provides a method for blocking writes and reads to specific ranges
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in the SPI flash when the Protected Ranges are enabled.
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PROTECTED_RANGE is used to specify if flash protection are enabled,
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the write protection enable bit and the read protection enable bit,
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and to specify the upper limit and lower base for each register
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Platform code is responsible to get the range base by PchGetSpiRegionAddresses routine,
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and set the limit and base accordingly.
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**/
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typedef struct {
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UINT32 WriteProtectionEnable : 1; ///< Write or erase is blocked by hardware. <b>0: Disable</b>; 1: Enable.
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UINT32 ReadProtectionEnable : 1; ///< Read is blocked by hardware. <b>0: Disable</b>; 1: Enable.
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UINT32 RsvdBits : 30; ///< Reserved
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/**
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The address of the upper limit of protection
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This is a left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison
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**/
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UINT16 ProtectedRangeLimit;
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/**
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The address of the upper limit of protection
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This is a left shifted address by 12 bits with address bits 11:0 are assumed to be 0
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**/
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UINT16 ProtectedRangeBase;
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} PROTECTED_RANGE;
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES];
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} PCH_FLASH_PROTECTION_CONFIG;
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#pragma pack (pop)
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#endif // _FLASH_PROTECTION_CONFIG_H_
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