/**@file
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ACPI DSDT table for SCS Controllers
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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If(LEqual(PCHV(), SPTL)) { // SCS available on PCH-LP only
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Scope(\_SB.PCI0) {
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//
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// SCS eMMC (PCI Mode)
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//
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Device(PEMC) {
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Name(_ADR, 0x001E0004)
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// Memory Region to access to the eMMC PCI Configuration Space
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OperationRegion(SCSR, PCI_Config, 0x00, 0x100)
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Field(SCSR, WordAcc, NoLock, Preserve) {
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Offset(R_PCH_SCS_DEV_PCS), // 0x84, PMCSR - Power Management Control and Status
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PSTA,32,
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Offset(R_PCH_SCS_DEV_PG_CONFIG), // 0xA2, Device PG config
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, 2,
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PGEN, 1 // [BIT2] PGE - PG Enable
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}
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Method(_PS0, 0, Serialized) {
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Store(0, PGEN) // Disable PG
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// Register address: 0xFD000000 SB offset | 0xC0<<16 PID_SCS | 0x0600 GPPRVRW1
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PCRA(PID_SCS, R_PCH_PCR_SCS_GPPRVRW1, 0x7FFFFFBA) // Clear bits 31, 6, 2, 0
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Sleep(2) // Wait 2ms
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// Register address: 0xFD000000 SB offset | 0xC0<<16 PID_SCS | 0x0600 GPPRVRW1
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PCRO(PID_SCS, R_PCH_PCR_SCS_GPPRVRW1, 0x80000045) // Set bits 31, 6, 2, 0
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And(PSTA, 0xFFFFFFFC, PSTA) // Set BIT[1:0] = 00b - Power State D0
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Store(PSTA, TEMP) // Read Back PMCSR
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}
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Method(_PS3, 0, Serialized) {
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Store(1, PGEN) // Enable PG
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Or(PSTA, 0x3, PSTA) // Set BIT[1:0] = 11b - Power State D3
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Store(PSTA, TEMP) // Read Back PMCSR
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}
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// _DSM x86 Device Specific Method
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// Arg0: UUID Unique function identifier
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// Arg1: Integer Revision Level
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// Arg2: Integer Function Index (0 = Return Supported Functions)
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// Arg3: Package Parameters
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Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) {
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If(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }
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ADBG(Concatenate("EMH4=",ToDecimalString(EMH4)))
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// Check the UUID
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If(LEqual(Arg0, ToUUID("f6c13ea5-65cd-461f-ab7a-29f7e8d5bd61"))) {
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// Check the revision
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If(LGreaterEqual(Arg1, Zero)) {
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//Switch statement based on the function index.
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Switch(ToInteger(Arg2)) {
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//
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// Function Index 0 the return value is a buffer containing
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// one bit for each function index, starting with zero.
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// Bit 0 - Indicates whether there is support for any functions other than function 0.
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// Bit 1 - Indicates support to clear power control register
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// Bit 2 - Indicates support to set power control register
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// Bit 3 - Indicates support to set 1.8V signalling
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// Bit 4 - Indicates support to set 3.3V signalling
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// Bit 5 - Indicates support for HS200 mode
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// Bit 6 - Indicates support for HS400 mode
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// Bit 9 - Indicates eMMC I/O Driver Strength
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//
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// On SPT, for eMMC we have to support functions for
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// HS200 and HS400 and I/O Driver Strength
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//
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Case(0) {
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//
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// The return value 0x261 (BIT6 set) for HS400 enabled and
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// 0x221 (BIT6 not set) when HS400 is disabled in Setup menu.
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//
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If(LEqual(EMH4, 1)) {
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Return(Buffer() {0x61, 0x02}) // HS400 support enabled
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}
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Return(Buffer() {0x21, 0x02}) // HS400 support disabled
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}
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//
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// Function index 5 - corresponds to HS200 mode
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// Return value from this function is used to program
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// the UHS Mode Select bits in Host Control 2.
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// 011b - corresponds to SDR104 and according to the
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// SD Host Controller Spec and this value is overloaded
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// to program the controller to select HS200 mode for eMMC.
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//
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Case(5) {
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Return(Buffer() {0x3})
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}
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//
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// Function index 6 - corresponds to HS400 mode
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// Return value from this function is used to program
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// the UHS Mode Select bits in Host Control 2.
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// 101b is a reserved value according to the SD Host
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// Controller Spec and we use this value for HS400 mode
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// selection.
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//
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Case(6) {
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Return(Buffer() {0x5})
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}
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//
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// Function index 9 - corresponds to I/O Driver Strength
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// Return value from this function represents the values
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// of the Driver Strength selection
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// (eMMC 5.01 Specification JESD84-B50.1, Table 186)
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// that shall be programmed by the Host Driver (OS)
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// as part of the Initialization flows.
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//
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Case(9) {
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Switch(EMDS) {
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Case(0x0) { Return(Buffer() {0x0}) } // 50 Ohm
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Case(0x1) { Return(Buffer() {0x1}) } // 33 Ohm
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Case(0x4) { Return(Buffer() {0x4}) } // 40 Ohm
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}
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}
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} // End - Switch(Arg2)
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}
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} // End - UUID check
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Return(Buffer() {0x0})
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} // End - _DSM
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Device (CARD) {
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Name (_ADR, 0x00000008)
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Method(_RMV, 0x0, NotSerialized) { Return (0) } // Device cannot be removed
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}
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} // Device(PEMC)
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//
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// SCS SD Card (PCI Mode)
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//
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Device(PSDC) {
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Name(_ADR, 0x001E0006)
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// Memory Region to access to the SDHC PCI Configuration Space
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OperationRegion(SCSR, PCI_Config, 0x00, 0x100)
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Field(SCSR, WordAcc, NoLock, Preserve) {
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Offset(R_PCH_SCS_DEV_PCS), // 0x84, PMCSR - Power Management Control and Status
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PSTA,32,
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Offset(R_PCH_SCS_DEV_PG_CONFIG), // 0xA2, Device PG config
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, 2,
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PGEN, 1 // [BIT2] PGE - PG Enable
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}
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Method(_PS0, 0, Serialized) {
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Store(0, PGEN) // Disable PG
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// Register address: 0xFD000000 SB offset | 0xC0<<16 PID_SCS | 0x0600 GPPRVRW1
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PCRA(PID_SCS, R_PCH_PCR_SCS_GPPRVRW1, 0xFFFFFE7A) // Clear bits 8, 7, 2, 0
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Sleep(2) // Wait 2ms
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// Register address: 0xFD000000 SB offset | 0xC0<<16 PID_SCS | 0x0600 GPPRVRW1
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PCRO(PID_SCS, R_PCH_PCR_SCS_GPPRVRW1, 0x00000185) // Set bits 8, 7, 2, 0
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And(PSTA, 0xFFFFFFFC, PSTA) // Set BIT[1:0] = 00b - Power State D0
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Store(PSTA, TEMP) // Read Back PMCSR
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}
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Method(_PS3, 0, Serialized) {
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Store(1, PGEN) // Enable PG
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Or(PSTA, 0x3, PSTA) // Set BIT[1:0] = 11b - Power State D3
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Store(PSTA, TEMP) // Read Back PMCSR
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}
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// _DSM x86 Device Specific Method
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// Arg0: UUID Unique function identifier
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// Arg1: Integer Revision Level
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// Arg2: Integer Function Index (0 = Return Supported Functions)
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// Arg3: Package Parameters
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Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) {
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If(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }
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// Check the UUID
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If(LEqual(Arg0, ToUUID("f6c13ea5-65cd-461f-ab7a-29f7e8d5bd61"))) {
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// Check the revision
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If(LGreaterEqual(Arg1, Zero)) {
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// Switch statement based on the function index.
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Switch(ToInteger(Arg2)) {
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//
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// Function Index 0 the return value is a buffer containing
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// one bit for each function index, starting with zero.
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// Bit 0 - Indicates whether there is support for any functions other than function 0.
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// Bit 1 - Indicates support to clear power control register
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// Bit 2 - Indicates support to set power control register
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// Bit 3 - Indicates support to set 1.8V signalling
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// Bit 4 - Indicates support to set 3.3V signalling
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// Bit 5 - Indicates support for HS200 mode
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// Bit 6 - Indicates support for HS400 mode
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// Bit 9 - Indicates eMMC I/O Driver Strength
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//
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// On SPT, for SD we have to support functions to
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// set 1.8V signalling and 3.3V signalling
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//
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Case(0) {
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Return (Buffer() {0x19})
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}
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//
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// Function Index 3: Set 1.8v signalling.
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// We put a sleep of 100ms in this method to
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// work around a known issue with detecting
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// UHS SD card on SPT. This is to compensate
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// for the SD VR slowness.
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//
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Case(3) {
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Sleep (100) // Sleep 100ms
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Return(Buffer(){0x00})
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}
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//
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// Function Index 4: Set 3.3v signalling.
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// We put a sleep of 100ms in this method to
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// work around a known issue with detecting
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// UHS SD card on SPT. This is to compensate
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// for the SD VR slowness.
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//
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Case(4) {
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Sleep (100) // Sleep 100ms
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Return(Buffer(){0x00})
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}
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} // End - Switch(Arg2)
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}
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} // End - UUID check
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Return(Buffer() {0x0})
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} // End _DSM
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}
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}
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}// End If(LEqual(PCHV(), SPTL)) - PCH-LP only
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