/**@file
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#define PCI_CARD_BASE_ADDR0 0x10
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#define PCI_CARD_BASE_ADDR1 0x14
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#define PCI_CARD_BASE_ADDR2 0x18
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#define PCI_CARD_BASE_ADDR3 0x1C
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#define PCI_CARD_BASE_ADDR4 0x20
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#define PCI_CARD_BASE_ADDR5 0x24
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#define VDID_OFFSET 0x0 // 32bit value
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#define LEDM_OFFSET 0x324 // bit 3 - DMI L1 Entry Disable Mask (DMIL1EDM)
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#define LDIS_OFFSET 0x50 //bit 4 - Link Disable (LD)
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#define DPGE_OFFSET 0x420 // bit 30 - Disabled, Detect, L23_Rdy State and Un-Configured PHY Lane Power Gating Enable (DLSULPPGE)
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#define LASX_OFFSET 0x52 // bit 13 - Link Active (LA)
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#define ROOTPORT_READ 0
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#define ROOTPORT_WRITE 1
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#define ENDPOINT_READ 2
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#define ENDPOINT_WRITE 3
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//RST Pcie Storage Remapped Base Address Index Value
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Name(PRBI, 0)
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//RST Pcie Storage Remapped Base Address Data Value
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Name(PRBD, 0)
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//RST Pcie Storage Endpoint Command Data
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Name(PCMD, 0)
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Name(RSTG, Package() { 0, 0, 0, 0 })
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Name(PWRG, Package() { 0, 0, 0, 0 })
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Name(SCLK, Package() { 0, 0, 0 })
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//RST Pcie Storage Cycle Router
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Name(NCRN, 0)
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//
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// Variables list to store corresponding value for different NVM device
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//
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Name(NITV, 0) // Interface Type
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Name(NPMV, 0) // Power Management Capability Pointer
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Name(NPCV, 0) // PCIe Capabilities Pointer
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Name(NL1V, 0) // L1SS Capability Pointer
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Name(ND2V, 0) // Endpoint L1SS Control Data2
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Name(ND1V, 0) // Endpoint L1SS Control Data1
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Name(NLRV, 0) // LTR Capability Pointer
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Name(NLDV, 0) // Endpoint LTR Data
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Name(NEAV, 0) // Endpoint LCTL Data
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Name(NEBV, 0) // Endpoint DCTL Data
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Name(NECV, 0) // Endpoint DCTL2 Data
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Name(NRAV, 0) // RootPort DCTL2 Data
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Name(NMBV, 0) // Endpoint unique MSI-X Table BAR
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Name(NMVV, 0) // Endpoint unique MSI-X Table BAR value
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Name(NPBV, 0) // Endpoint unique MSI-X PBA BAR
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Name(NPVV, 0) // Endpoint unique MSI-X PBA BAR value
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Name(NRPN, 0) // Assigned Root Port number
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Name(MXIE, 0)
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Name(ISD3, 0) // Is device in D3 state
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//
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// Restore of Remapped Device and Hidden Root Port
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// This method is called after the endpoint is to be power ungated (D3-cold to D0 unitialized)
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//
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Method(CNRS, 0, Serialized)
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{
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Store("[ACPI RST] Restore Remapped Device and Hidden RP context |start", Debug)
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ADBG(Concatenate("CNRSs ", ToDecimalString(Timer())))
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//
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// Return if RST Pcie Storage Remapping is disabled
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//
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If(LEqual(NITV,0))
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{
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Return()
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}
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//
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// Clear all BARs in Remapped Device
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//
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RDCA(NCRN,PCI_CARD_BASE_ADDR0,0x0,0x0,ENDPOINT_WRITE)
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RDCA(NCRN,PCI_CARD_BASE_ADDR1,0x0,0x0,ENDPOINT_WRITE)
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RDCA(NCRN,PCI_CARD_BASE_ADDR2,0x0,0x0,ENDPOINT_WRITE)
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RDCA(NCRN,PCI_CARD_BASE_ADDR3,0x0,0x0,ENDPOINT_WRITE)
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RDCA(NCRN,PCI_CARD_BASE_ADDR4,0x0,0x0,ENDPOINT_WRITE)
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RDCA(NCRN,PCI_CARD_BASE_ADDR5,0x0,0x0,ENDPOINT_WRITE)
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//
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// Restore remapped BAR and Endpoint CMD
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//
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RDCA(NCRN,PRBI,0x0,PRBD,ENDPOINT_WRITE)
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RDCA(NCRN,0x4,0xFFFFFFF8,PCMD,ENDPOINT_WRITE)
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//
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// Restore of Remapped Device L1 Substate if this Capability is supported
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//
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If(LNotEqual(NL1V,0))
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{
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RDCA(NCRN,Add(NL1V,0x0C),0xFFFFFF00,ND2V,ENDPOINT_WRITE)
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RDCA(NCRN,Add(NL1V,0x08),0x0000000F,And(ND1V,0xFFFFFFF0),ENDPOINT_WRITE)
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RDCA(NCRN,Add(NL1V,0x08),0xFFFFFFFF,ND1V,ENDPOINT_WRITE)
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}
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//
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// Restore of Remapped Device LTR if this Capability is supported
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//
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If(LNotEqual(NLRV,0))
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{
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RDCA(NCRN,Add(NLRV,0x04),0xFFFFFFFF,NLDV,ENDPOINT_WRITE)
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}
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//
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// Restore of Remapped Device Link Control's "Enable Clock Power Management" field and "Common Clock Configuration" field
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//
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RDCA(NCRN,Add(NPCV,0x10),0xFFFFFEBF,And(NEAV,0xFFFC),ENDPOINT_WRITE)
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//
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// Restore of Remapped Device Device Control 2 field
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//
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RDCA(NCRN,Add(NPCV,0x28),0xFFFFFBFF,NECV,ENDPOINT_WRITE)
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//
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// Restore of Remapped Device Device Control field
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//
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RDCA(NCRN,Add(NPCV,0x8),0xFFFFFF1F,NEBV,ENDPOINT_WRITE)
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//
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// Restore of Hidden Root Port field
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//
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RDCA(NCRN,0x68,0xFFFFFBFF,NRAV,ROOTPORT_WRITE)
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//
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// Check CCC bit
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// If this bit is 1, perform link retrain by setting the "Retrain Link" bit
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//
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If(LEqual(And(NEAV,0x40),0x40))
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{
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RDCA(NCRN,0x50,0xFFFFFFDF,0x20,ROOTPORT_WRITE)
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//
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// Poll PCIe Link Active status till it is active
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//
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ADBG(Concatenate("CNRSw ", ToDecimalString(Timer())))
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while(LEqual(And(RDCA(NCRN,0x52,0x0,0x0,ROOTPORT_READ),0x2000),0))
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{
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Stall(10)
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}
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}
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ADBG(Concatenate("CNRSx ", ToDecimalString(Timer())))
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//
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// Restore of Remapped Device Link Control's "Active State Link PM Control" field
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//
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RDCA(NCRN,Add(NPCV,0x10),0xFFFFFFFC,And(NEAV,0x0003),ENDPOINT_WRITE)
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//
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// Restore of Remapped Device related device BAR for the MSI-X Table BAR if the device supports unique MSI-X Table BAR
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//
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If(LNotEqual(NMVV,0))
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{
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RDCA(NCRN,NMBV,0x0,NMVV,ENDPOINT_WRITE)
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}
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//
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// Restore of Remapped Device related device BAR for the MSI-X PBA BAR if the device supports unique MSI-X PBA BAR
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//
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If(LNotEqual(NPVV,0))
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{
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RDCA(NCRN,NPBV,0x0,NPVV,ENDPOINT_WRITE)
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}
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ADBG(Concatenate("CNRSe ", ToDecimalString(Timer())))
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Store("[ACPI RST] Restore Remapped Device and Hidden RP context |complete", Debug)
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}
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