/**@file
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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External(\_SB.PCI0.HDAS.PS0X, MethodObj)
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External(\_SB.PCI0.HDAS.PS3X, MethodObj)
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External(\_SB.PCI0.HDAS.PPMS, MethodObj)
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External(HIDW, MethodObj)
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External(HIWC, MethodObj)
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//
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// High Definition Audio Controller - Device 31, Function 3
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//
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Device(HDAS)
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{
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Name(_ADR, 0x001F0003)
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//
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// Define a Memory Region that will allow access to the HDA PCI Configuration Space
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//
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OperationRegion(HDAR, PCI_Config, 0x00, 0x100)
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Field(HDAR,WordAcc,NoLock,Preserve) {
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VDID,32 // 0x00, VID DID
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}
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//
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// Byte access for PMCS field to avoid race condition on device D-state
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//
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Field(HDAR,ByteAcc,NoLock,Preserve) {
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Offset(R_PCH_HDA_PCS), // 0x54, Power Management Control and Status Register
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,8,
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PMEE,1, // PME Enable
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,6,
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PMES,1 // PME Status
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}
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Name(_S0W, 3) // Device can wake itself from D3 in S0
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Method(_DSW, 3) { Store(Arg0, PMEE) } // Device wake enable
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Method(_PRW, 0) { Return(GPRW(0x6D, 4)) } // Can wakeup from S4 state
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// GPE handler for HDA, this is part of _Lxx handler for bus 0 PME
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Method(GPEH) {
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If(LEqual(VDID, 0xFFFFFFFF)) {
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Return()
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}
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If(LAnd(PMEE, PMES)) {
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ADBG("HDAS GPEH")
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Store(1, PMES) // clear PME Status
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Notify(HDAS, 0x02)
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}
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}
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// D0 Method for HD-A Controller
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Method(_PS0, 0, Serialized)
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{
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//
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// Call platform HDAS PS0 method if present
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//
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If(CondRefOf(\_SB.PCI0.HDAS.PS0X)) {
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\_SB.PCI0.HDAS.PS0X()
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}
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}
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// D3 Method for HD-A Controller
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Method(_PS3, 0, Serialized)
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{
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//
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// Call platform HDAS PS3 method if present
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//
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If(CondRefOf(\_SB.PCI0.HDAS.PS3X)) {
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\_SB.PCI0.HDAS.PS3X()
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}
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}
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// NHLT Table memory descriptor, returned from _DSM
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Name(NBUF, ResourceTemplate () {
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// NHLT table address (_MIN = NHLT 64bit pointer, _MAX = _MIN + _LEN - 1) and length (_LEN)
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QWordMemory (ResourceConsumer, , MinNotFixed, MaxNotFixed, NonCacheable, ReadOnly,
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0x1, // AddressGranularity
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0x0000000000000000, // AddressMinimum _MIN
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0x0000000000000000, // AddressMaximum _MAX
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0x0,
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0x0, // RangeLength _LEN
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, , NHLT, AddressRangeACPI,)
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})
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Method(_INI) {
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// Update resource according to NVS
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ADBG("HDAS _INI")
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// Set NHLT base address and length
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CreateQWordField(NBUF, ^NHLT._MIN, NBAS)
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CreateQWordField(NBUF, ^NHLT._MAX, NMAS)
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CreateQWordField(NBUF, ^NHLT._LEN, NLEN)
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Store(NHLA, NBAS)
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Add(NHLA, Subtract(NHLL, 1), NMAS)
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Store(NHLL, NLEN)
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}
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Method(_DSM, 0x4, NotSerialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) {
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// Arg0 - UUID: A69F886E-6CEB-4594-A41F-7B5DCE24C553 (Buffer)
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// Arg1 - Revision ID: 0x01 (Integer)
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// Arg2 - Function Index: 0x0 - 0x3 (Integer) - See below for details.
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// Arg3 - Depends on Function Index - See below for details.
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// Return - Depends on Function Index - See below for details.
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ADBG("HDAS _DSM")
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if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }
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// Verify UUID
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If (LEqual(Arg0, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))) {
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Switch(ToInteger(Arg2)) {
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// Function 0: Function Support Query
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// Arg2 - Function Index: 0x00 (Integer)
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// Arg3: Unused
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// Return: Bitmask of functions supported. (Buffer)
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Case(0) {
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// Supports function 0 - 3
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Return(Buffer(One) { 0x0F })
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}
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// Function 1: Query Non HD Audio Descriptor Table
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// Used by the Intel Offload Engine Driver to discover the
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// non HD Audio devices supported by the Audio DSP.
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// Arg2 - Function Index: 0x01 (Integer)
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// Arg3 - Unused
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// Return - ACPI Table describing the non HD Audio links and devices supported by the ADSP (ResourceBuffer)
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Case(1) {
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ADBG("_DSM Fun 1 NHLT")
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// NBUF - Memory Resource Descriptor buffer with address and length of NHLT
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Return(NBUF)
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}
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// Function 2: Query Feature Mask
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// Used by the Intel Offload Engine Driver to retrieve a bitmask
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// of features allowable on this platform.
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// Arg2 - Function Index: 0x02 (Integer)
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// Arg3: Unused
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// Return: Bitmask of supported features.
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Case (2) {
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ADBG("_DSM Fun 2 FMSK")
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// Bit 0 == '1', WoV is supported, Bit 0 == '0', WoV not supported
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// Bit 1 == '1', BT Sideband is supported, Bit 1 == '0', BT not supported
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// Bit 2 == '1', codec based VAD support allowable
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// Bit 3 - 4 Reserved
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// Bit 5 == '1', BT Intel HFP SCO is supported
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// Bit 6 == '1', BT Intel A2DP is supported
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// Bit 7 == '1', DSP based speech pre-processing disabled
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// Bit 8 == '1', Windows Voice Activation, Bit 8 == '0', Intel Wake on Voice
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// Bit 9 - 31 Reserved, shall be set to '0'
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// ADFM - NVS AudioDSP Feature Bit Mask updated from PchPolicy
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Return(ADFM)
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}
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// Function 3: Query Pre/Post Processing Module Support
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// Used by the Intel Offload Engine Driver to determine if a
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// specified PP Module is allowed to be supported on this platform
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// Arg2 - Function Index: 0x03 (Integer)
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// Arg3 - UUID: Specifies the UUID of the PP module to check (Buffer)
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// Return - TRUE if PP Module supported, else FALSE.
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Case (3) {
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ADBG("_DSM Fun 3 PPMS")
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If(CondRefOf(\_SB.PCI0.HDAS.PPMS)) {
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// Call platform method PPMS to check if 3rd Party IP module with given GUID (Arg3) is supported
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Return(\_SB.PCI0.HDAS.PPMS (Arg3))
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}
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Return(0) // Is not supported
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}
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Default {
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// Function not supported (Arg2)
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ADBG("_DSM Fun NOK")
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Return(Buffer(One) { 0x00 })
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}
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} // Switch(Arg2) End
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} // If(Arg0, UUID) End
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//-------------------------------------------
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// HID Wake up Event solution
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//-------------------------------------------
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If(CondRefOf(HIWC)) {
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If(HIWC(Arg0)) {
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If(CondRefOf(HIDW)) {
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Return (HIDW(Arg0, Arg1, Arg2, Arg3))
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}
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}
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}
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// UUID not supported (Arg0)
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ADBG("_DSM UUID NOK")
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Return(Buffer() {0})
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} // _DSM End
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} // end "High Definition Audio Controller"
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