/** @file
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Implementation of Fsp SA Policy Initialization.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PeiFspPolicyInitLib.h>
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#include <Ppi/SiPolicy.h>
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#include <ConfigBlock/MemoryConfig.h>
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#include <Library/IoLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/SmbusLib.h>
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#include <Library/MmPciLib.h>
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#include <Library/ConfigBlockLib.h>
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#include <Library/PcdLib.h>
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#include <IndustryStandard/Pci.h>
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#include <MrcSpdData.h>
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#include <PchAccess.h>
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#include <Ppi/FirmwareVolume.h>
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#include <Pi/PiFirmwareFile.h>
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#include <Pi/PiPeiCis.h>
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#define MAX_SPD_PAGE_COUNT (2)
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#define MAX_SPD_PAGE_SIZE (256)
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#define MAX_SPD_SIZE (MAX_SPD_PAGE_SIZE * MAX_SPD_PAGE_COUNT)
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#define SPD_PAGE_ADDRESS_0 (0x6C)
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#define SPD_PAGE_ADDRESS_1 (0x6E)
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#define SPD_DDR3_SDRAM_TYPE_OFFSET (0x02)
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#define SPD_DDR3_SDRAM_TYPE_NUMBER (0x0B)
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#define SPD_DDR4_SDRAM_TYPE_NUMBER (0x0C)
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#define SPD_LPDDR3_SDRAM_TYPE_NUMBER (0xF1)
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#define SPD_JEDEC_LPDDR3_SDRAM_TYPE_NUMBER (0x0F)
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#define XMP_ID_STRING (0x4A0C)
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#define SPD3_MANUF_START (117)
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#define SPD3_MANUF_END (127)
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#define SPD4_MANUF_START (320)
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#define SPD4_MANUF_END (328)
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#define SPDLP_MANUF_START (320)
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#define SPDLP_MANUF_END (328)
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GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdDdr3Table[] = {
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{ 0, 1, (1 << SpdCold),},
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{ 2, 2, (1 << SpdCold) | (1 << SpdFast),},
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{ 3, 41, (1 << SpdCold),},
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{ 60, 63, (1 << SpdCold),},
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{ SPD3_MANUF_START, SPD3_MANUF_END, (1 << SpdCold) | (1 << SpdFast),},
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{ 128, 145, (1 << SpdCold),},
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#ifdef SUPPORT_SPD_CRC
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{ 39, 59, (1 << SpdCold),},
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{ 64, 125, (1 << SpdCold),},
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#endif
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{ 176, 179, (1 << SpdCold),},
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{ 180, 184, (1 << SpdCold),},
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{ 185, 215, (1 << SpdCold),},
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{ 220, 250, (1 << SpdCold),},
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};
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GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdDdr4Table[] = {
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{ 0, 1, (1 << SpdCold),},
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{ 2, 2, (1 << SpdCold) | (1 << SpdFast),},
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{ 3, 40, (1 << SpdCold),},
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{ 117, 131, (1 << SpdCold),},
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{ SPD4_MANUF_START, SPD4_MANUF_END, (1 << SpdCold) | (1 << SpdFast),},
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{ 329, 348, (1 << SpdCold),},
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#ifdef SUPPORT_SPD_CRC
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{ 32, 119, (1 << SpdCold),},
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{ 126, 255, (1 << SpdCold),},
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{ 349, 383, (1 << SpdCold),},
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#endif
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{ 384, 387, (1 << SpdCold),},
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{ 388, 389, (1 << SpdCold),},
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{ 393, 431, (1 << SpdCold),},
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{ 440, 478, (1 << SpdCold),},
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};
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GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdLpddrTable[] = {
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{ 0, 1, (1 << SpdCold),},
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{ 2, 2, (1 << SpdCold) | (1 << SpdFast),},
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{ 3, 32, (1 << SpdCold),},
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{ 120, 130, (1 << SpdCold),},
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{ SPDLP_MANUF_START, SPDLP_MANUF_END, (1 << SpdCold) | (1 << SpdFast),},
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{ 329, 348, (1 << SpdCold),},
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#ifdef SUPPORT_SPD_CRC
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{ 31, 121, (1 << SpdCold),},
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{ 126, 255, (1 << SpdCold),},
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{ 349, 383, (1 << SpdCold),},
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#endif
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{ 384, 387, (1 << SpdCold),},
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{ 388, 389, (1 << SpdCold),},
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{ 393, 431, (1 << SpdCold),},
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{ 440, 478, (1 << SpdCold),},
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};
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/**
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Read the SPD data over the SMBus, at the specified SPD address, starting at
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the specified starting offset and read the given amount of data.
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@param[in] SpdAddress - SPD SMBUS address
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@param[in, out] Buffer - Buffer to store the data.
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@param[in] Start - Starting SPD offset
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@param[in] Size - The number of bytes of data to read and also the size of the buffer.
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@param[in, out] Page - The final page that is being pointed to.
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@retval EFI_SUCCESS if the read is successful, otherwise error status.
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**/
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static
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EFI_STATUS
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InternalDoSpdRead (
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IN const UINT8 SpdAddress,
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IN OUT UINT8 *const Buffer,
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IN const UINT16 Start,
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IN UINT16 Size,
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IN OUT UINT8 *const Page
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)
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{
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EFI_STATUS EfiStatus;
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BOOLEAN PageUpdate;
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UINT16 Count;
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UINT16 Index;
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EfiStatus = EFI_DEVICE_ERROR;
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if ((Buffer != NULL) && (Start < MAX_SPD_SIZE) && ((Start + Size) < MAX_SPD_SIZE)) {
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Count = 0;
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PageUpdate = FALSE;
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while (Size--) {
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Index = Start + Count;
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if ((Index / MAX_SPD_PAGE_SIZE) != *Page) {
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*Page = (UINT8) (Index / MAX_SPD_PAGE_SIZE);
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PageUpdate = TRUE;
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}
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Index %= MAX_SPD_PAGE_SIZE;
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if (PageUpdate == TRUE) {
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PageUpdate = FALSE;
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SmBusWriteDataByte ((*Page == 0) ? SPD_PAGE_ADDRESS_0 : SPD_PAGE_ADDRESS_1, 0, &EfiStatus);
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}
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Buffer[Count] = SmBusReadDataByte (SpdAddress | ((UINT32) Index << 8), &EfiStatus);
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if (EFI_SUCCESS != EfiStatus) {
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Buffer[Count] = 0;
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break;
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}
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Count++;
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}
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EfiStatus = EFI_SUCCESS;
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}
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return (EfiStatus);
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}
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/**
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See if there is valid XMP SPD data.
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@param[in] Debug - Mrc debug structure.
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@param[in, out] Spd - Mrc SPD structure.
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@param[in] XmpStart - The current offset in the SPD.
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@retval TRUE if valid, FALSE in not.
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**/
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static
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BOOLEAN
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InternalVerifyXmp (
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IN OUT MrcSpd *const Spd,
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IN const UINT16 XmpStart
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)
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{
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SPD_EXTREME_MEMORY_PROFILE_HEADER *Header1;
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SPD_EXTREME_MEMORY_PROFILE_HEADER_2_0 *Header2;
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BOOLEAN Xmp;
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Xmp = FALSE;
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switch (((UINT8 *)Spd)[2]) {
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case SPD_DDR3_SDRAM_TYPE_NUMBER:
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Header1 = &Spd->Ddr3.Xmp.Header;
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if (XmpStart == ((UINT32) (Header1) - (UINT32) Spd)) {
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Xmp = TRUE;
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if ((Header1->XmpRevision.Data & 0xFE) == 0x12) {
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return (TRUE);
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} else {
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Header1->XmpId = 0;
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Header1->XmpOrgConf.Data = 0;
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Header1->XmpRevision.Data = 0;
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}
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}
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break;
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case SPD_DDR4_SDRAM_TYPE_NUMBER:
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Header2 = &Spd->Ddr4.EndUser.Xmp.Header;
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if (XmpStart == ((UINT32) (Header2) - (UINT32) Spd)) {
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Xmp = TRUE;
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if ((Header2->XmpRevision.Data) == 0x20) {
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return (TRUE);
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} else {
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Header2->XmpId = 0;
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Header2->XmpOrgConf.Data = 0;
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Header2->XmpRevision.Data = 0;
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}
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}
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break;
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case SPD_JEDEC_LPDDR3_SDRAM_TYPE_NUMBER:
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case SPD_LPDDR3_SDRAM_TYPE_NUMBER:
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return (TRUE);
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default:
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return (FALSE);
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}
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if (!Xmp) {
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return (TRUE);
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}
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return (FALSE);
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}
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/**
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Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data structure.
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The SPD data locations read is controlled by the current boot mode.
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@param[in] BootMode - The current MRC boot mode.
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@param[in] Address - SPD SmBus address offset.
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@param[in] Buffer - Buffer that contains the data read from the SPD.
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@param[in] SpdDdr3Table - Indicates which SPD bytes to read.
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@param[in] SpdDdr3TableSize - Size of SpdDdr3Table in bytes.
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@param[in] SpdDdr4Table - Indicates which SPD bytes to read.
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@param[in] SpdDdr4TableSize - Size of SpdDdr4Table in bytes.
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@param[in] SpdLpddrTable - Indicates which SPD bytes to read.
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@param[in] SpdLpddrTableSize - Size of SpdLpddrTable in bytes.
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@retval TRUE if the read is successful, otherwise FALSE on error.
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**/
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BOOLEAN
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InternalGetSpdData (
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IN SPD_BOOT_MODE BootMode,
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IN UINT8 Address,
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IN OUT UINT8 *Buffer,
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IN UINT8 *SpdDdr3Table,
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IN UINT32 SpdDdr3TableSize,
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IN UINT8 *SpdDdr4Table,
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IN UINT32 SpdDdr4TableSize,
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IN UINT8 *SpdLpddrTable,
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IN UINT32 SpdLpddrTableSize
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)
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{
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const SPD_OFFSET_TABLE *Tbl;
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const SPD_OFFSET_TABLE *TableSelect;
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EFI_STATUS Status;
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UINT32 Byte;
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UINT32 Stop;
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UINT8 Page;
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Page = (UINT8) (~0);
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Status = InternalDoSpdRead (Address, &Buffer[SPD_DDR3_SDRAM_TYPE_OFFSET], 2, 1, &Page);
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if (EFI_SUCCESS == Status) {
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switch (Buffer[SPD_DDR3_SDRAM_TYPE_OFFSET]) {
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case SPD_DDR3_SDRAM_TYPE_NUMBER:
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case SPD_LPDDR3_SDRAM_TYPE_NUMBER:
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default:
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TableSelect = (SPD_OFFSET_TABLE *) SpdDdr3Table;
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Stop = (SpdDdr3TableSize / sizeof (SPD_OFFSET_TABLE));
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break;
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case SPD_DDR4_SDRAM_TYPE_NUMBER:
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TableSelect = (SPD_OFFSET_TABLE *) SpdDdr4Table;
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Stop = (SpdDdr4TableSize / sizeof (SPD_OFFSET_TABLE));
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break;
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case SPD_JEDEC_LPDDR3_SDRAM_TYPE_NUMBER:
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TableSelect = (SPD_OFFSET_TABLE *) SpdLpddrTable;
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Stop = (SpdLpddrTableSize / sizeof (SPD_OFFSET_TABLE));
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break;
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}
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for (Byte = 0; (EFI_SUCCESS == Status) && (Byte < Stop); Byte++) {
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Tbl = &TableSelect[Byte];
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if ((1 << BootMode) & Tbl->BootMode) {
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Status = InternalDoSpdRead (Address, &Buffer[Tbl->Start], Tbl->Start, Tbl->End - Tbl->Start + 1, &Page);
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if (Status == EFI_SUCCESS) {
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if (SpdCold == BootMode) {
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if (FALSE == InternalVerifyXmp ((MrcSpd *) Buffer, Tbl->Start)) {
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break;
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}
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}
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} else {
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break;
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}
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}
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}
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}
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return ((EFI_SUCCESS == Status) ? TRUE : FALSE);
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}
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/**
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Initialize the Smbus PPI and program the Smbus BAR
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@retval EFI_SUCCESS The function completes successfully
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@retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
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**/
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EFI_STATUS
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InternalInitializePchSmbus (
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VOID
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)
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{
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UINTN SmbusRegBase;
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SmbusRegBase = MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_SMBUS,
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PCI_FUNCTION_NUMBER_PCH_SMBUS
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);
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///
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/// Since PEI has no PCI enumerator, set the BAR & I/O space enable ourselves
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///
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MmioAndThenOr32 (SmbusRegBase + R_PCH_SMBUS_BASE, B_PCH_SMBUS_BASE_BAR, PcdGet16 (PcdSmbusBaseAddress));
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MmioOr8 (SmbusRegBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_IO_SPACE);
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///
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/// Reset the SMBus host controller
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///
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MmioOr8 (SmbusRegBase + R_PCH_SMBUS_HOSTC, B_PCH_SMBUS_HOSTC_SSRESET);
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///
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/// Enable the SMBus host controller
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///
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MmioAndThenOr8 (
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SmbusRegBase + R_PCH_SMBUS_HOSTC,
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(UINT8)(~(B_PCH_SMBUS_HOSTC_SMI_EN | B_PCH_SMBUS_HOSTC_I2C_EN)),
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B_PCH_SMBUS_HOSTC_HST_EN
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);
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///
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/// Clear Status Register before anyone uses the interfaces
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///
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IoWrite8 (PcdGet16(PcdSmbusBaseAddress) + R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL);
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return EFI_SUCCESS;
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}
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/**
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Update Spd Data
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@param[in][out] FspmUpd Pointer to FSP UPD Data.
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@param[in] MemConfigNoCrc Pointer to Mem Config No Crc.
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@param[in] MiscPeiPreMemConfig Pointer to Misc Config.
|
|
@retval EFI_SUCCESS The function completes successfully
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@retval Other The function fail
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**/
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VOID
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EFIAPI
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InternalUpdateSpdData (
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IN OUT FSPM_UPD *FspmUpd,
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IN MEMORY_CONFIG_NO_CRC *MemConfigNoCrc,
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IN SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig
|
)
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{
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UINT8 Socket;
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UINT8 *SpdData;
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InternalInitializePchSmbus ();
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DEBUG ((DEBUG_INFO, "Updating UPD:Memory Spd Pointers...\n"));
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if (FspmUpd == NULL || MemConfigNoCrc == NULL) {
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DEBUG ((DEBUG_ERROR, "EFI_INVALID_PARAMETER.\n"));
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DEBUG ((DEBUG_ERROR, "Fail to access SPD from SiPolicyPpi\n"));
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return;
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}
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if (*((UINT32 *)MiscPeiPreMemConfig->SpdAddressTable) != 0x0) {
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//
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// Update MemConfigNoCrc->SpdData->SpdData
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//
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for (Socket = 0; Socket < SA_MC_MAX_SOCKETS; Socket++) {
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SpdData = (UINT8 *)((UINT32)MemConfigNoCrc->SpdData->SpdData + (Socket * SA_MC_MAX_SPD_SIZE));
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InternalGetSpdData (
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0,
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MiscPeiPreMemConfig->SpdAddressTable[Socket],
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(UINT8 *)SpdData,
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(UINT8 *)&mSpdDdr3Table,
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sizeof(mSpdDdr3Table),
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(UINT8 *)&mSpdDdr4Table,
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sizeof(mSpdDdr4Table),
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(UINT8 *)&mSpdLpddrTable,
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sizeof(mSpdLpddrTable)
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);
|
}
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}
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FspmUpd->FspmConfig.MemorySpdPtr00 = (UINT32)MemConfigNoCrc->SpdData->SpdData;
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FspmUpd->FspmConfig.MemorySpdPtr01 = (UINT32)MemConfigNoCrc->SpdData->SpdData + (1 * SA_MC_MAX_SPD_SIZE);
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FspmUpd->FspmConfig.MemorySpdPtr10 = (UINT32)MemConfigNoCrc->SpdData->SpdData + (2 * SA_MC_MAX_SPD_SIZE);
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FspmUpd->FspmConfig.MemorySpdPtr11 = (UINT32)MemConfigNoCrc->SpdData->SpdData + (3 * SA_MC_MAX_SPD_SIZE);
|
|
DEBUG ((DEBUG_INFO, "UPD:MemorySpdPtr Updated\n"));
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}
|
|
/**
|
Performs FSP SA PEI Policy initialization in pre-memory.
|
|
@param[in][out] FspmUpd Pointer to FSP UPD Data.
|
|
@retval EFI_SUCCESS FSP UPD Data is updated.
|
@retval EFI_NOT_FOUND Fail to locate required PPI.
|
@retval Other FSP UPD Data update process fail.
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**/
|
EFI_STATUS
|
EFIAPI
|
PeiFspSaPolicyInitPreMem (
|
IN OUT FSPM_UPD *FspmUpd
|
)
|
{
|
EFI_STATUS Status;
|
SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
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MEMORY_CONFIGURATION *MemConfig;
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MEMORY_CONFIG_NO_CRC *MemConfigNoCrc;
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SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
|
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//
|
// Locate SiPreMemPolicyPpi
|
//
|
SiPreMemPolicyPpi = NULL;
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MiscPeiPreMemConfig = NULL;
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MemConfig = NULL;
|
MemConfigNoCrc = NULL;
|
|
|
Status = PeiServicesLocatePpi(
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&gSiPreMemPolicyPpiGuid,
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0,
|
NULL,
|
(VOID **) &SiPreMemPolicyPpi
|
);
|
ASSERT_EFI_ERROR (Status);
|
if (EFI_ERROR (Status) == FALSE) {
|
Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
|
ASSERT_EFI_ERROR (Status);
|
Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc);
|
ASSERT_EFI_ERROR (Status);
|
Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMemoryConfigGuid, (VOID *) &MemConfig);
|
ASSERT_EFI_ERROR (Status);
|
}
|
|
//
|
// Update UPD:DqPinsInterleaved
|
//
|
FspmUpd->FspmConfig.DqPinsInterleaved = (UINT8)MemConfig->DqPinsInterleaved;
|
|
//
|
// Update UPD:DqPinsInterleaved
|
//
|
FspmUpd->FspmConfig.CaVrefConfig = MemConfig->CaVrefConfig;
|
|
//
|
// Update UPD:MemorySpdPtrXX
|
//
|
InternalUpdateSpdData (FspmUpd, MemConfigNoCrc, MiscPeiPreMemConfig);
|
|
//
|
// Update UPD:MemorySpdDataLen
|
//
|
FspmUpd->FspmConfig.MemorySpdDataLen = SA_MC_MAX_SPD_SIZE;
|
|
//
|
// Update UPD:PlatformMemorySize
|
//
|
//
|
// @todo: This value is used since #183932. Revisit.
|
//
|
FspmUpd->FspmConfig.PlatformMemorySize = MemConfigNoCrc->PlatformMemorySize;
|
FspmUpd->FspmConfig.SaGv = MemConfig->SaGv;
|
FspmUpd->FspmConfig.RMT = (UINT8) MemConfig->RMT;
|
FspmUpd->FspmConfig.DdrFreqLimit = MemConfig->DdrFreqLimit;
|
|
FspmUpd->FspmConfig.SpdProfileSelected = MemConfig->SpdProfileSelected;
|
FspmUpd->FspmConfig.VddVoltage = MemConfig->VddVoltage;
|
FspmUpd->FspmConfig.RefClk = MemConfig->RefClk;
|
FspmUpd->FspmConfig.Ratio = MemConfig->Ratio;
|
FspmUpd->FspmConfig.OddRatioMode = (UINT8) MemConfig->OddRatioMode;
|
FspmUpd->FspmConfig.tCL = (UINT8) MemConfig->tCL;
|
FspmUpd->FspmConfig.tCWL = (UINT8) MemConfig->tCWL;
|
FspmUpd->FspmConfig.tFAW = MemConfig->tFAW;
|
FspmUpd->FspmConfig.tRAS = MemConfig->tRAS;
|
FspmUpd->FspmConfig.tRCDtRP = (UINT8) MemConfig->tRCDtRP;
|
FspmUpd->FspmConfig.tREFI = MemConfig->tREFI;
|
FspmUpd->FspmConfig.tRFC = MemConfig->tRFC;
|
FspmUpd->FspmConfig.tRRD = (UINT8) MemConfig->tRRD;
|
FspmUpd->FspmConfig.tRTP = (UINT8) MemConfig->tRTP;
|
FspmUpd->FspmConfig.tWR = (UINT8) MemConfig->tWR;
|
FspmUpd->FspmConfig.tWTR = (UINT8) MemConfig->tWTR;
|
FspmUpd->FspmConfig.NModeSupport = MemConfig->NModeSupport;
|
FspmUpd->FspmConfig.DllBwEn0 = MemConfig->DllBwEn0;
|
FspmUpd->FspmConfig.DllBwEn1 = MemConfig->DllBwEn1;
|
FspmUpd->FspmConfig.DllBwEn2 = MemConfig->DllBwEn2;
|
FspmUpd->FspmConfig.DllBwEn3 = MemConfig->DllBwEn3;
|
FspmUpd->FspmConfig.EvLoader = (UINT8) MemConfig->EvLoader;
|
|
//
|
// Update UPD:SmramMask
|
//
|
if (MemConfig != NULL) {
|
FspmUpd->FspmConfig.SmramMask = MemConfig->SmramMask;
|
}
|
|
return EFI_SUCCESS;
|
}
|
|
/**
|
Performs FSP SA PEI Policy initialization.
|
|
@param[in][out] FspsUpd Pointer to FSP UPD Data.
|
|
@retval EFI_SUCCESS FSP UPD Data is updated.
|
@retval EFI_NOT_FOUND Fail to locate required PPI.
|
@retval Other FSP UPD Data update process fail.
|
**/
|
EFI_STATUS
|
EFIAPI
|
PeiFspSaPolicyInit (
|
IN OUT FSPS_UPD *FspsUpd
|
)
|
{
|
EFI_STATUS Status;
|
SI_POLICY_PPI *SiPolicyPpi;
|
GRAPHICS_PEI_CONFIG *GtConfig;
|
VTD_CONFIG *Vtd;
|
//
|
// Locate SiPolicyPpi
|
//
|
SiPolicyPpi = NULL;
|
Status = PeiServicesLocatePpi(
|
&gSiPolicyPpiGuid,
|
0,
|
NULL,
|
(VOID **)&SiPolicyPpi
|
);
|
if ((Status == EFI_SUCCESS) && (SiPolicyPpi != NULL)) {
|
GtConfig = NULL;
|
Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid, (VOID *) &GtConfig);
|
ASSERT_EFI_ERROR (Status);
|
|
Vtd = NULL;
|
Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gVtdConfigGuid, (VOID *) &Vtd);
|
ASSERT_EFI_ERROR (Status);
|
|
}
|
|
DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiSaPolicy\n"));
|
if (GtConfig != NULL) {
|
//
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// For FSP, FspsUpd->FspsConfig.PeiGraphicsPeimInit is always enabled as default.
|
//
|
FspsUpd->FspsConfig.PeiGraphicsPeimInit = (UINT8) GtConfig->PeiGraphicsPeimInit; // SA: InternalOnly: For Internal validation we still need to enable both Enable/Disable Cases
|
|
//
|
// Update UPD: VBT & LogoPtr
|
//
|
FspsUpd->FspsConfig.GraphicsConfigPtr = (UINT32) GtConfig->GraphicsConfigPtr;
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DEBUG(( DEBUG_INFO, "VbtPtr from GraphicsPeiConfig is 0x%x\n", FspsUpd->FspsConfig.GraphicsConfigPtr));
|
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FspsUpd->FspsConfig.LogoPtr = (UINT32) GtConfig->LogoPtr;
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FspsUpd->FspsConfig.LogoSize = GtConfig->LogoSize;
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DEBUG(( DEBUG_INFO, "LogoPtr from PeiFspSaPolicyInit GraphicsPeiConfig is 0x%x\n", FspsUpd->FspsConfig.LogoPtr));
|
DEBUG(( DEBUG_INFO, "LogoSize from PeiFspSaPolicyInit GraphicsPeiConfig is 0x%x\n", FspsUpd->FspsConfig.LogoSize));
|
|
|
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}
|
if (Vtd != NULL) {
|
FspsUpd->FspsConfig.X2ApicOptOut = (UINT8) Vtd->X2ApicOptOut;
|
FspsUpd->FspsConfig.VtdBaseAddress[0] = Vtd->BaseAddress[0];
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FspsUpd->FspsConfig.VtdBaseAddress[1] = Vtd->BaseAddress[1];
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FspsUpd->FspsTestConfig.VtdDisable = (UINT8) Vtd->VtdDisable;
|
}
|
return EFI_SUCCESS;
|
}
|
