/** @file
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Source code file for Platform Init Pre-Memory PEI module
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Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Uefi.h>
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#include <PiPei.h>
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#include <PchAccess.h>
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#include <SaPolicyCommon.h>
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#include <CpuAccess.h>
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#include <SaAccess.h>
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#include <IndustryStandard/Pci30.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/HobLib.h>
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#include <Library/PcdLib.h>
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#include <Library/TimerLib.h>
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#include <Library/MmPciLib.h>
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#include <Library/CpuPlatformLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/PchCycleDecodingLib.h>
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#include <Library/PchPcrLib.h>
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#include <Library/PchPmcLib.h>
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#include <Ppi/MemoryDiscovered.h>
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#include <Ppi/FirmwareVolumeInfo.h>
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#include <Include/Library/ConfigBlockLib.h>
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#include <Library/PeiServicesTablePointerLib.h>
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#include <Library/PchSerialIoLib.h>
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/**
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Early Silicon initialization
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**/
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VOID
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EarlySiliconInit (
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VOID
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)
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{
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UINT16 Data16;
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UINT8 Data8;
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UINTN LpcBaseAddress;
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UINTN P2sbBase;
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LpcBaseAddress = MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_LPC,
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PCI_FUNCTION_NUMBER_PCH_LPC
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);
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///
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/// Program bar
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///
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P2sbBase = MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_P2SB,
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PCI_FUNCTION_NUMBER_PCH_P2SB
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);
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MmioWrite32 (P2sbBase + R_PCH_P2SB_SBREG_BAR, PCH_PCR_BASE_ADDRESS);
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MmioOr8 (P2sbBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
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///
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/// Program ACPI BASE
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///
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PchAcpiBaseSet (PcdGet16 (PcdAcpiBaseAddress));
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///
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/// Program PWRM BASE
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///
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PchPwrmBaseSet (PCH_PWRM_BASE_ADDRESS);
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///
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/// Program TCO BASE if it is present and not locked
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///
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if (PchIsTcoBaseSetValid ()) {
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PchTcoBaseSet (PcdGet16 (PcdTcoBaseAddress));
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}
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///
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/// LPC I/O Configuration
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///
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PchLpcIoDecodeRangesSet (
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(V_PCH_LPC_IOD_LPT_378 << N_PCH_LPC_IOD_LPT) |
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(V_PCH_LPC_IOD_COMB_3E8 << N_PCH_LPC_IOD_COMB) |
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(V_PCH_LPC_IOD_COMA_3F8 << N_PCH_LPC_IOD_COMA)
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);
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PchLpcIoEnableDecodingSet (
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B_PCH_LPC_IOE_ME2 |
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B_PCH_LPC_IOE_SE |
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B_PCH_LPC_IOE_ME1 |
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B_PCH_LPC_IOE_KE |
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B_PCH_LPC_IOE_HGE |
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B_PCH_LPC_IOE_LGE |
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B_PCH_LPC_IOE_FDE |
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B_PCH_LPC_IOE_PPE |
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B_PCH_LPC_IOE_CBE |
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B_PCH_LPC_IOE_CAE
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);
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///
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/// Enable the upper 128-byte bank of RTC RAM
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///
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PchPcrAndThenOr32 (PID_RTC, R_PCH_PCR_RTC_CONF, (UINT32)~0, B_PCH_PCR_RTC_CONF_UCMOS_EN);
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///
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/// Disable the Watchdog timer expiration from causing a system reset
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///
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PchPcrAndThenOr32 (PID_ITSS, R_PCH_PCR_ITSS_GIC, (UINT32)~0, B_PCH_PCR_ITSS_GIC_AME);
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///
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/// Halt the TCO timer
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///
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Data16 = IoRead16 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO1_CNT);
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Data16 |= B_PCH_TCO_CNT_TMR_HLT;
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IoWrite16 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO1_CNT, Data16);
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///
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/// Clear the Second TO status bit
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///
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IoWrite8 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO2_STS, B_PCH_TCO2_STS_SECOND_TO);
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///
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/// Disable SERR NMI and IOCHK# NMI in port 61
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///
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Data8 = IoRead8 (R_PCH_NMI_SC);
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Data8 |= (B_PCH_NMI_SC_PCI_SERR_EN | B_PCH_NMI_SC_IOCHK_NMI_EN);
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IoWrite8 (R_PCH_NMI_SC, Data8);
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PchPcrAndThenOr32 (PID_ITSS, R_PCH_PCR_ITSS_GIC, (UINT32)~B_PCH_PCR_ITSS_GIC_AME, 0);
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//
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// Program timer 1 as refresh timer
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//
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IoWrite8 (0x43, 0x54);
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IoWrite8 (0x41, 0x12);
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}
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// @todo: It should be moved Policy Init.
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/**
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Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal inversion registers
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**/
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VOID
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SiliconInit (
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VOID
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)
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{
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UINT16 Data16;
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UINT8 Data8;
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UINTN LpcBaseAddress;
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UINT16 ABase;
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UINT16 Pm1Sts;
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UINT32 Pm1Cnt;
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LpcBaseAddress = MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_LPC,
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PCI_FUNCTION_NUMBER_PCH_LPC
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);
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///
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/// LPC I/O Configuration
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///
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PchLpcIoDecodeRangesSet (
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(V_PCH_LPC_IOD_LPT_378 << N_PCH_LPC_IOD_LPT) |
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(V_PCH_LPC_IOD_COMB_3E8 << N_PCH_LPC_IOD_COMB) |
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(V_PCH_LPC_IOD_COMA_3F8 << N_PCH_LPC_IOD_COMA)
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);
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PchLpcIoEnableDecodingSet (
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B_PCH_LPC_IOE_ME2 |
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B_PCH_LPC_IOE_SE |
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B_PCH_LPC_IOE_ME1 |
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B_PCH_LPC_IOE_KE |
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B_PCH_LPC_IOE_HGE |
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B_PCH_LPC_IOE_LGE |
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B_PCH_LPC_IOE_FDE |
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B_PCH_LPC_IOE_PPE |
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B_PCH_LPC_IOE_CBE |
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B_PCH_LPC_IOE_CAE
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);
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///
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/// Enable the upper 128-byte bank of RTC RAM
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///
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PchPcrAndThenOr32 (PID_RTC, R_PCH_PCR_RTC_CONF, (UINT32)~0, B_PCH_PCR_RTC_CONF_UCMOS_EN);
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///
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/// Disable the Watchdog timer expiration from causing a system reset
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///
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PchPcrAndThenOr32 (PID_SMB, R_PCH_PCR_SMBUS_GC, (UINT32)~0, B_PCH_PCR_SMBUS_GC_NR);
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///
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/// Halt the TCO timer
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///
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Data16 = IoRead16 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO1_CNT);
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Data16 |= B_PCH_TCO_CNT_TMR_HLT;
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IoWrite16 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO1_CNT, Data16);
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///
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/// Clear the Second TO status bit
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///
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IoWrite8 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO2_STS, B_PCH_TCO2_STS_SECOND_TO);
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///
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/// Disable SERR NMI and IOCHK# NMI in port 61
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///
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Data8 = IoRead8 (R_PCH_NMI_SC);
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Data8 |= (B_PCH_NMI_SC_PCI_SERR_EN | B_PCH_NMI_SC_IOCHK_NMI_EN);
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IoWrite8 (R_PCH_NMI_SC, Data8);
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///
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/// Clear all pending SMI. On S3 clear power button enable so it will not generate an SMI.
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///
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IoWrite16 (PcdGet16 (PcdAcpiBaseAddress) + R_PCH_ACPI_PM1_EN, 0);
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IoWrite32 (PcdGet16 (PcdAcpiBaseAddress) + R_PCH_ACPI_GPE0_EN_127_96, 0);
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///----------------------------------------------------------------------------------
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///
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/// BIOS should check the WAK_STS bit in PM1_STS[15] (PCH register ABASE+00h) before memory
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/// initialization to determine if ME has reset the system while the host was in a sleep state.
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/// If WAK_STS is not set, BIOS should ensure a non-sleep exit path is taken by overwriting
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/// PM1_CNT[12:10] (PCH register ABASE+04h) to 111b to force an s5 exit.
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///
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PchAcpiBaseGet (&ABase);
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Pm1Sts = IoRead16 (ABase + R_PCH_ACPI_PM1_STS);
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if ((Pm1Sts & B_PCH_ACPI_PM1_STS_WAK) == 0) {
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Pm1Cnt = IoRead32 (ABase + R_PCH_ACPI_PM1_CNT);
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Pm1Cnt |= V_PCH_ACPI_PM1_CNT_S5;
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IoWrite32 (ABase + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
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}
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}
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