/** @file
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Source code file for Platform Init PEI module
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Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Uefi.h>
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#include <PiPei.h>
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#include <CpuRegs.h>
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#include <PchAccess.h>
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#include <Library/IoLib.h>
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#include <Library/HobLib.h>
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#include <Library/PcdLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PchInfoLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/MmPciLib.h>
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#include <IndustryStandard/Pci30.h>
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#include <Library/PchCycleDecodingLib.h>
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#include <Library/GpioLib.h>
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#include <Ppi/EndOfPeiPhase.h>
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#include <Guid/SmramMemoryReserve.h>
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#include <Library/ConfigBlockLib.h>
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#include <Ppi/SiPolicy.h>
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#include <SaPolicyCommon.h>
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#include <Guid/FirmwareFileSystem2.h>
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#include <GpioPinsSklLp.h>
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#include <Library/TimerLib.h>
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/**
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Clear any SMI status or wake status left from boot.
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@retval EFI_SUCCESS The function completed successfully.
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**/
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EFI_STATUS
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ClearIchSmiAndWake (
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VOID
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)
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{
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EFI_STATUS Status;
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EFI_BOOT_MODE BootMode;
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UINT16 ABase;
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UINT16 Pm1Sts;
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UINT32 Pm1Cnt;
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UINT32 Data32;
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UINT32 Gpe0Sts;
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UINT32 SmiSts;
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UINT16 DevActSts;
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UINT16 TcoBase;
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UINT16 Tco1Sts;
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UINT16 LpcDeviceId;
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UINTN LanBaseAddress;
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UINT16 LanPmcs;
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Status = PeiServicesGetBootMode (&BootMode);
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ASSERT_EFI_ERROR (Status);
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if (BootMode == BOOT_ON_S3_RESUME) {
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return EFI_SUCCESS;
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}
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PchAcpiBaseGet (&ABase);
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PchTcoBaseGet (&TcoBase);
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//
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// Read the ACPI registers
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//
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Pm1Sts = IoRead16 (ABase + R_PCH_ACPI_PM1_STS);
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Pm1Cnt = IoRead32 (ABase + R_PCH_ACPI_PM1_CNT);
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Gpe0Sts = IoRead32 (ABase + R_PCH_ACPI_GPE0_STS_127_96);
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SmiSts = IoRead32 (ABase + R_PCH_SMI_STS);
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Data32 = 0;
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//
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// Before clear B_PCH_ACPI_GPE0_STS_127_96_PME_B0, PMES bit of internal device must be cleared at first.
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//
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Data32 = (Gpe0Sts & B_PCH_ACPI_GPE0_STS_127_96_PME_B0);
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if (Data32 != 0) {
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//
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// Check if Internal LAN waked up system
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//
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LanBaseAddress = MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_LAN,
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PCI_FUNCTION_NUMBER_PCH_LAN
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);
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LanPmcs = MmioRead16 (LanBaseAddress + R_PCH_LAN_PMCS);
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if ((LanPmcs & B_PCH_LAN_PMCS_PMES) != 0) {
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//
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// Clear PMES bit
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//
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MmioOr16 (LanBaseAddress + R_PCH_LAN_PMCS, B_PCH_LAN_PMCS_PMES);
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DEBUG ((DEBUG_INFO, "Clear LAN PMES bit!\n"));
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}
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}
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LpcDeviceId = GetLpcDid ();
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//
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// Clear any SMI or wake state from the boot
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//
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Pm1Sts |=
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(
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B_PCH_ACPI_PM1_STS_WAK |
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B_PCH_ACPI_PM1_STS_PRBTNOR |
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B_PCH_ACPI_PM1_STS_RTC |
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B_PCH_ACPI_PM1_STS_PWRBTN |
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B_PCH_ACPI_PM1_STS_GBL |
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B_PCH_ACPI_PM1_STS_TMROF
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);
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Gpe0Sts |=
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(
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B_PCH_ACPI_GPE0_STS_127_96_PME_B0 |
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B_PCH_ACPI_GPE0_STS_127_96_PME |
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B_PCH_ACPI_GPE0_STS_127_96_PCI_EXP |
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B_PCH_ACPI_GPE0_STS_127_96_RI |
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B_PCH_ACPI_GPE0_STS_127_96_SMB_WAK |
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B_PCH_ACPI_GPE0_STS_127_96_TC0SCI |
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B_PCH_ACPI_GPE0_STS_127_96_HOT_PLUG |
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B_PCH_ACPI_GPE0_STS_127_96_LAN_WAKE
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);
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//
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// PCH Desktop
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//
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if (IS_PCH_LPC_DEVICE_ID_MOBILE (LpcDeviceId)) {
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Gpe0Sts |= B_PCH_ACPI_GPE0_STS_127_96_BATLOW;
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}
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SmiSts |=
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(
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B_PCH_SMI_STS_SMBUS |
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B_PCH_SMI_STS_PERIODIC |
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B_PCH_SMI_STS_TCO |
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B_PCH_SMI_STS_MCSMI |
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B_PCH_SMI_STS_SWSMI_TMR |
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B_PCH_SMI_STS_APM |
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B_PCH_SMI_STS_ON_SLP_EN |
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B_PCH_SMI_STS_BIOS
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);
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//
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// Write them back
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//
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IoWrite16 (ABase + R_PCH_ACPI_PM1_STS, Pm1Sts);
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IoWrite32 (ABase + R_PCH_ACPI_GPE0_STS_127_96, Gpe0Sts);
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IoWrite32 (ABase + R_PCH_SMI_STS, SmiSts);
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DevActSts = IoRead16 (ABase + R_PCH_DEVACT_STS);
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Tco1Sts = IoRead16 (TcoBase + R_PCH_TCO1_STS);
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DevActSts |=
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(
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B_PCH_DEVACT_STS_KBC |
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B_PCH_DEVACT_STS_PIRQDH |
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B_PCH_DEVACT_STS_PIRQCG |
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B_PCH_DEVACT_STS_PIRQBF |
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B_PCH_DEVACT_STS_PIRQAE
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);
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Tco1Sts |=
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(
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B_PCH_TCO1_STS_DMISERR |
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B_PCH_TCO1_STS_DMISMI |
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B_PCH_TCO1_STS_DMISCI |
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B_PCH_TCO1_STS_BIOSWR |
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B_PCH_TCO1_STS_NEWCENTURY |
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B_PCH_TCO1_STS_TIMEOUT |
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B_PCH_TCO1_STS_TCO_INT |
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B_PCH_TCO1_STS_SW_TCO_SMI
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);
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//
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// clear GPI SMI STS
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//
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GpioClearAllGpiSmiSts ();
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IoWrite16 (TcoBase + R_PCH_TCO1_STS, Tco1Sts);
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//
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// We do not want to write 1 to clear INTRD_DET bit.
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//
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IoWrite16 ((UINTN) (TcoBase + R_PCH_TCO2_STS), (UINT16) ~B_PCH_TCO2_STS_INTRD_DET);
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IoWrite16 (ABase + R_PCH_DEVACT_STS, DevActSts);
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//
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// Clear Power Failure (PWR_FLR), It was used to check S3_Resume State.
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//
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// MmioOr8 (
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// LpcBaseAddress + R_PCH_PMC_GEN_PMCON_B,
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// B_PCH_PMC_GEN_PMCON_B_PWR_FLR
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// );
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return EFI_SUCCESS;
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}
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/**
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Late Silicon Initialization
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**/
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VOID
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LateSiliconInit (
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VOID
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)
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{
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ClearIchSmiAndWake ();
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}
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