/** @file
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PCIe Initialization Library header file
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCIE_INIT_LIB_H_
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#define _PCIE_INIT_LIB_H_
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#include <Uefi/UefiBaseType.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/PostCodeLib.h>
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#include <Library/HobLib.h>
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#include <Library/IoLib.h>
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#include <Library/TimerLib.h>
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#include <Library/PeiServicesLib.h>
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#include <IndustryStandard/Pci30.h>
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#include <Library/MmPciLib.h>
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#include <Library/GpioLib.h>
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#ifdef PCIE_X32_SUPPORT
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#define PCIE_MAX_LANE 32
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#else
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#define PCIE_MAX_LANE 16
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#endif
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#define PCIE_ROOT_PORT_BITMAP_LENGTH 8
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#define PCIE_SWEQ_MAX_PRESETS 11
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#ifndef STALL_ONE_MICRO_SECOND
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#define STALL_ONE_MICRO_SECOND 1
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#endif
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#ifndef STALL_ONE_MILLI_SECOND
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#define STALL_ONE_MILLI_SECOND 1000
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#endif
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///
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/// PCIe Root Port description data structure, used as the interface between low
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/// level and high level
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///
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typedef struct {
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UINT8 MaxCapableSpeed;
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UINT8 MaxCapableWidth;
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BOOLEAN EnableMargin;
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BOOLEAN SkipMargin;
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BOOLEAN FoundUsableTxEq;
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UINT8 ActiveLaneListLength;
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UINT8 ActiveLaneList[PCIE_MAX_LANE];
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} PCIE_PORT_SWEQ_DATA;
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typedef struct {
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UINT8 Bus;
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UINT8 Device;
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UINT8 Function;
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UINTN ConfigSpaceBase;
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UINT8 PcieCapOffset;
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UINT8 MaxPortWidth;
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UINT8 MaxPortSpeed;
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UINT8 MaxPortLaneListLength;
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UINT8 MaxPortLaneList[PCIE_MAX_LANE];
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///
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/// Variables below this line will only contain valid data after the PCIe link
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/// is enabled and completes training
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///
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BOOLEAN EndpointPresent;
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UINT32 EndpointVendorIdDeviceId;
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UINT8 EndpointMaxLinkSpeed;
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UINT8 EndpointMaxLinkWidth;
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PCIE_PORT_SWEQ_DATA SwEqData;
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} PCIE_PORT_INFO;
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///
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/// Data structure for passing static equalization data for programming
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///
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typedef struct {
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PCIE_PORT_INFO *PciePort;
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UINT8 RootPortPresets[PCIE_MAX_LANE];
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UINT8 EndpointPresets[PCIE_MAX_LANE];
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UINT8 EndpointHints[PCIE_MAX_LANE];
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} PCIE_PORT_EQS;
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///
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/// Input Configuration Parameters for Software Equalization Support
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///
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typedef struct {
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BOOLEAN EnableGpioPerstSupport;
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GPIO_PAD GpioPad;
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BOOLEAN GpioActiveHigh;
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} PCIE_SWEQ_GPIO_CONFIG;
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typedef struct {
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PCIE_PORT_INFO *PciePort;
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UINT8 StaticEndpointPresets[PCIE_MAX_LANE];
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UINT8 LastBootBestPresets[PCIE_MAX_LANE];
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UINT32 LastBootEndpointVendorIdDeviceId;
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PCIE_SWEQ_GPIO_CONFIG GpioConfig;
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BOOLEAN EnableSwEq;
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} PCIE_SWEQ_PORT_INPUT;
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typedef struct {
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PCIE_SWEQ_PORT_INPUT *PerPortInputParameters;
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UINT8 PerPortInputParametersLength;
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BOOLEAN HaveDataFromLastBoot;
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UINT8 PresetsToTest[PCIE_SWEQ_MAX_PRESETS];
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UINT8 PresetsToTestLength;
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BOOLEAN AlwaysAttemptSwEq;
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UINTN JitterDwellTime;
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UINT16 JitterErrorTarget;
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UINTN VocDwellTime;
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UINT16 VocErrorTarget;
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BOOLEAN EnableVocTest;
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BOOLEAN EnableBdatScoreSchema;
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} PCIE_SWEQ_INPUT_PARAMETERS;
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///
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/// Data Output from Software Equalization
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///
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typedef struct {
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INT32 MarginScore[PCIE_MAX_LANE];
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UINT8 Preset;
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} PCIE_SWEQ_PRESET_SCORE;
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typedef struct {
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PCIE_PORT_INFO *PciePort;
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INT32 TempMarginData[PCIE_MAX_LANE];
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UINT8 BestPresets[PCIE_MAX_LANE];
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INT32 BestScores[PCIE_MAX_LANE];
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PCIE_SWEQ_PRESET_SCORE PresetScores[PCIE_SWEQ_MAX_PRESETS];
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} PCIE_SWEQ_PORT_OUTPUT;
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typedef struct {
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PCIE_SWEQ_PORT_OUTPUT *PortOutputList;
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UINT8 PortOutputListLength;
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BOOLEAN DeferredPlatformResetRequired;
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} PCIE_SWEQ_OUTPUT;
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typedef enum {
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LaneLevelRxJitter,
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PortLevelRxJitter,
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VocCorners,
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MarginTestTypeMax
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} MARGIN_TEST_TYPE;
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typedef struct _PCIE_SI_LOW_LEVEL_FUNCTION_CALLS PCIE_SI_LOW_LEVEL_FUNCTION_CALLS;
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///
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/// PCIe Initialization Library Generic High Level Function Calls
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///
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/**
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The PCIe Software Equalization algorithm. Provides an adaptive EQ Phase 3
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implementation in software.
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@param[in] PcieAccess - Low level function table
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@param[in] PciePorts - PCIe Root Ports to wait for
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@param[in] PciePortsLength - Length of the PciePorts array
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@param[in] InputParameters - Configuration options for SW EQ
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@param[out] OutputData - The data that the algorithm generated
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**/
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VOID
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PcieGen3SoftwareEqualization (
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IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *PcieAccess,
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IN PCIE_PORT_INFO *PciePorts,
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IN UINT8 PciePortsLength,
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IN PCIE_SWEQ_INPUT_PARAMETERS *InputParameters,
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OUT PCIE_SWEQ_OUTPUT *OutputData
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);
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/**
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Waits for the Data Link Layer on all given root ports to reach the DL_Active state.
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The user passes a fail mask that indicates which root ports to check. The function
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will update the fail mask to indicate which root ports successfully trained.
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The fail mask is a bitmap based on PciePorts array indices. The array must be
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of length 8 or greater since the PciePorts array can have at most 256 entries.
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@param[in] PcieAccess - Low level function table
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@param[in] PciePorts - PCIe Root Ports to wait for
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@param[in] PciePortsLength - Length of the PciePorts array
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@param[in] ForceCheck - TRUE to ignore current FailMask and check all root ports
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@param[in, out] FailMask - Bitmap of root ports to check. Returns bitmap indicating which root ports
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failed to reach DL_Active. Array must be of length 8 or greater!
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**/
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VOID
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EFIAPI
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WaitForDataLinkLayerLinkActiveOnAllPorts (
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IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *PcieAccess,
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IN PCIE_PORT_INFO *PciePorts,
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IN UINT8 PciePortsLength,
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IN BOOLEAN ForceCheck,
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IN OUT UINT32 *FailMask ///< [PCIE_ROOT_PORT_BITMAP_LENGTH]
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);
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/**
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This function prints the time required for DL_Active to be set. Quits after 100 msec.
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@param[in] This - Low level function table
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@param[in] PciePort - PCIe Root Port
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**/
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VOID
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WaitForDataLinkLayerLinkActive (
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IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *PcieAccess,
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IN PCIE_PORT_INFO *PciePort
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);
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/**
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Computes the Pre-Cursor, Cursor, and Post-Cursor from a preset
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@param[in] Preset - Preset to compute coefficients for
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@param[in] FullSwing - The full swing of the transmitter
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@param[out] PreCursor - Computed Pre-Cursor
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@param[out] Cursor - Computed Cursor
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@param[out] PostCursor - Computed Post-Cursor
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**/
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VOID
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GetCoefficientsFromPreset (
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IN UINT8 Preset,
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IN UINT8 FullSwing,
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OUT UINT8 *PreCursor,
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OUT UINT8 *Cursor,
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OUT UINT8 *PostCursor
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);
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/**
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Checks for link speed and width downgrades
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@param[in] PcieAccess - Low level function table
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@param[in] PciePort - PCIe Root Port
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@param[in] OriginalLinkSpeed - Original Speed of the Link
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@param[in] OriginalLinkWidth - Original Width of the Link
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**/
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BOOLEAN
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LinkIsDowngraded (
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IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *PcieAccess,
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IN PCIE_PORT_INFO *PciePort,
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IN UINT8 OriginalLinkSpeed,
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IN UINT8 OriginalLinkWidth
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);
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///
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/// PCIe Initialization Library Generic Low Level Function Calls
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/// All of these functions can be implemented using only PCIe specification
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/// level details. However, it is possible to override the default
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/// implementation provided by this library with a Silicon Specific one if needed
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///
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/**
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This function detects if an endpoint is attached to each given root port and
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if so, reads data from the endpoint and fills in the remaining fields of the
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PCIE_PORT_INFO structure that could not be filled before initial link training
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@param[in] This - Low level function table
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@param[out] PciePorts - Array of PCIe Root Ports
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@param[out] PciePortsLength - Length of the PciePorts array
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**/
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typedef
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VOID
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(EFIAPI *PCIE_DETECT_ENDPOINT_PRESENCE)(
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IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
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IN PCIE_PORT_INFO *PciePorts,
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IN UINT8 PciePortsLength
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);
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/**
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Gets the PCIe Capability Structure Pointer
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@param[in] This - Low level function table
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@param[in] PciePort - PCIe Root Port
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@retval Offset to the PCIe Capability Structure
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**/
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typedef
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UINT8
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(EFIAPI *PCIE_GET_PCIE_CAP_OFFSET)(
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IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
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IN PCIE_PORT_INFO *PciePort
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);
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/**
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Checks if the Data Link Layer is in DL_Active state on the given root port
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@param[in] This - Low level function table
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@param[in] PciePort - Root Port to check for DL_Active
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@retval TRUE - Data Link Layer is in DL_Active state
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@retval FALSE - Data Link Layer is NOT in DL_Active state
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**/
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typedef
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BOOLEAN
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(EFIAPI *PCIE_DATA_LINK_LAYER_LINK_ACTIVE)(
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IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
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IN PCIE_PORT_INFO *PciePort
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);
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/**
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Returns the current value of the PCIe Slot Status Presence Detect bit
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@param[in] This - Low level function table
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@param[in] PciePort - PCIe Root Port
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@retval Slot Presence Detect bit state
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**/
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typedef
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BOOLEAN
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(EFIAPI *PCIE_GET_SLOT_PRESENCE_DETECT)(
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IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
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IN PCIE_PORT_INFO *PciePort
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);
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/**
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Set the Link Disable bit in the PCIe Link Control Register
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@param[in] This - Low level function table
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@param[in] PciePort - PCIe Root Port
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@param[in] LinkDisable - New value for link disable bit
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**/
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typedef
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VOID
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(EFIAPI *PCIE_SET_LINK_DISABLE)(
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IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
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IN PCIE_PORT_INFO *PciePort,
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IN BOOLEAN LinkDisable
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);
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/**
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Retrain the PCIe link
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@param[in] This - Low level function table
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@param[in] PciePort - PCIe Root Port
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**/
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typedef
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VOID
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(EFIAPI *PCIE_RETRAIN_LINK)(
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IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
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IN PCIE_PORT_INFO *PciePort
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);
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/**
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Get Negotiated Link Width
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@param[in] This - Low level function table
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@param[in] PciePort - PCIe Root Port
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**/
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typedef
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UINT8
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(EFIAPI *PCIE_GET_NEGOTIATED_WIDTH)(
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IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
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IN PCIE_PORT_INFO *PciePort
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);
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/**
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Get Current Link Speed
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@param[in] This - Low level function table
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@param[in] PciePort - PCIe Root Port
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**/
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typedef
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UINT8
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(EFIAPI *PCIE_GET_CURRENT_LINK_SPEED)(
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IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
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IN PCIE_PORT_INFO *PciePort
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);
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///
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/// PCIe Initialization Library Silicon Specific Low Level Function Calls
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/// Enables Abstraction of Silicon details keeping this library generic
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///
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/**
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This function determines if the silicon implements the PCIe bus interface
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that this instance of PCIE_SI_LOW_LEVEL_FUNCTION_CALLS is intended for.
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@retval TRUE - Silicon supports the bus interface
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@retval FALSE - otherwise
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**/
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typedef
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BOOLEAN
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(EFIAPI *PCIE_EXISTS)(
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IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This
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);
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/**
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This function determines the topology of the PCIe bus interface that is being
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initialized using silicon defined mechanisms. The PciePorts pointer must
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point to a pre-allocated array which is capable of containing the maximum
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number of root ports that this function will return. Generally this is done
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by a component specific entrypoint that can allocate the array on the stack
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using a fixed size appropriate for the HW. If this needs to be called from
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generic code, the generic code must allocate a buffer that can contain 256
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entries (which should be avoided.)
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@param[in] This - Low level function table
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@param[out] PciePorts - Array of Detected PCIe Root Ports
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@param[out] PciePortsLength - Length of the PciePorts array
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**/
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typedef
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VOID
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(EFIAPI *PCIE_GET_ROOT_PORTS)(
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IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
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OUT PCIE_PORT_INFO *PciePorts,
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OUT UINT8 *PciePortsLength
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);
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/**
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Programs static equalization settings for the given list of PCIe root ports.
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The PCIE_PORT_EQs structure is laid out such that the Root Port preset for
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PHYSICAL lane number PciePortEqs->PciePort->MaxPortLaneList[0] is
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PciePortEqs->RootPortPresets[0]. Note that physical lane numbers may not
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start at or include zero. Package pin 0 may not be mapped to a given Root Port
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@param[in] This - Low level function table
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@param[in] PciePortEqs - Array of Root Ports + Eqs to program
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@param[in] PciePortEqsLength - Number of Root Ports to program
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**/
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typedef
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VOID
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(EFIAPI *PCIE_PROGRAM_STATIC_GEN3_EQ)(
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IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
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IN PCIE_PORT_EQS *PciePortEqs,
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IN UINT8 PciePortEqsLength
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);
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/**
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Sets Gen3 Equalization Phase 2 Bypass for all given Root Ports
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@param[in] This - Low level function table
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@param[in] PciePorts - PCIe Root Ports to program Phase2 for
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@param[in] PciePortsLength - Length of the PciePorts array
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@param[in] BypassPhase2 - TRUE to enable Phase2 bypass, FALSE otherwise
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@retval EFI_SUCCESS - Phase 2 bypass was successful
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@retval EFI_UNSUPPORTED - Hardware does not support the given Phase2 bypass request
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**/
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typedef
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EFI_STATUS
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(EFIAPI *PCIE_SET_GEN3_PHASE2_BYPASS)(
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IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
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IN PCIE_PORT_INFO *PciePorts,
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IN UINT8 PciePortsLength,
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IN BOOLEAN BypassPhase2
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);
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/**
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This function reports a PCIe controller's link status
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@param[in] This - Low level function table
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@param[in] PciePort - PCIe Root Port
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**/
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typedef
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VOID
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(EFIAPI *PCIE_REPORT_LINK_STATUS)(
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IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
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IN PCIE_PORT_INFO *PciePort
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);
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///
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/// PCIe Link Recovery Functions
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///
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/**
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Wait until link is up.
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@param[in] This - Low level function table
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@param[in] PciePort - PCIe Root Port
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@retval EFI_SUCCESS - Completed successfully before timeout
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@retval EFI_TIMEOUT - Timed out
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**/
|
typedef
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EFI_STATUS
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(EFIAPI *PCIE_WAIT_FOR_L0)(
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IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
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IN PCIE_PORT_INFO *PciePort
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);
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/**
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Get Target Link Speed
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@param[in] This - Low level function table
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@param[in] PciePort - PCIe Root Port
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**/
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typedef
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UINT8
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(EFIAPI *PCIE_GET_TARGET_LINK_SPEED)(
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IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
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IN PCIE_PORT_INFO *PciePort
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);
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/**
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Set Target Link Speed
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@param[in] This - Low level function table
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@param[in] PciePort - PCIe Root Port
|
@param[in] TargetLinkSpeed - Target Link Speed
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**/
|
typedef
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VOID
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(EFIAPI *PCIE_SET_TARGET_LINK_SPEED)(
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IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
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IN PCIE_PORT_INFO *PciePort,
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IN UINT8 TargetLinkSpeed
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);
|
|
/**
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Resets the endpoint connected to the given root port by directly pulsing the
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PERST# signal. The minimum assertion time, T_PERST (100 usec), is defined in
|
the PCIe CEM Specification.
|
|
@param[in] This - Low level function table
|
@param[in] PciePort - PCIe Root Port
|
@param[in] InputParameters - SW EQ Input Parameters
|
|
@retval EFI_SUCCESS - GPIO set successfully
|
@retval EFI_UNSUPPORTED - GPIO is not supported
|
@retval EFI_INVALID_PARAMETER - GPIO pin number is invalid
|
@retval EFI_TIMEOUT - Link did not train after pulsing PERST#
|
**/
|
typedef
|
EFI_STATUS
|
(EFIAPI *PCIE_RESET_ENDPOINT_PERST)(
|
IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
|
IN PCIE_PORT_INFO *PciePort,
|
IN PCIE_SWEQ_INPUT_PARAMETERS *InputParameters
|
);
|
|
/**
|
This function asserts/deasserts a GPIO that controls PERST#. The minimum
|
assertion time, T_PERST (100 usec), is defined in the PCIe CEM Specification.
|
|
@param[in] This - Low level function table
|
@param[in] PciePort - PCIe Root Port
|
@param[in] InputParameters - SW EQ Input Parameters
|
@param[in] AssertPerst - TRUE to assert PERST#, FALSE to deassert
|
|
@retval EFI_SUCCESS - GPIO set successfully
|
@retval EFI_UNSUPPORTED - GPIO is not supported
|
@retval EFI_INVALID_PARAMETER - GPIO pin number is invalid
|
**/
|
typedef
|
EFI_STATUS
|
(EFIAPI *PCIE_SET_PERST)(
|
IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
|
IN PCIE_PORT_INFO *PciePort,
|
IN PCIE_SWEQ_INPUT_PARAMETERS *InputParameters,
|
IN BOOLEAN AssertPerst
|
);
|
|
/**
|
Recovers a link width downgrade back to the original width. Generally this
|
doesn't need to be called directly since EnsureLinkIsHealthy() checks link
|
width in addition to other link health checks.
|
|
@param[in] This - Low level function table
|
@param[in] PciePort - PCIe Root Port
|
@param[in] OriginalLinkWidth - Original Link Width
|
|
@retval EFI_SUCCESS - Link is running at the correct width
|
@retval EFI_DEVICE_ERROR - Unable to correct link width downgrade
|
@retval EFI_TIMEOUT - Link did not successfully retrain
|
**/
|
typedef
|
EFI_STATUS
|
(EFIAPI *PCIE_RECOVER_LINK_WIDTH)(
|
IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
|
IN PCIE_PORT_INFO *PciePort,
|
IN UINT8 OriginalLinkWidth
|
);
|
|
/**
|
This function sets a GPIO to a particular level.
|
|
@param[in] This - Low level function table
|
@param[in] GpioPad - PCH GPIO Pad
|
@param[in] Level - 0 = Low, 1 = High
|
|
@retval EFI_SUCCESS - GPIO set successfully
|
@retval EFI_UNSUPPORTED - GPIO is not supported
|
@retval EFI_INVALID_PARAMETER - GPIO pin number is invalid
|
**/
|
typedef
|
EFI_STATUS
|
(EFIAPI *PCIE_SET_PCH_GPIO)(
|
IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
|
IN GPIO_PAD GpioPad,
|
IN UINT8 Level
|
);
|
|
/**
|
Check the status of the given PCIe link, detect and correct and downgrades
|
|
@param[in] This - Low level function table
|
@param[in] InputParameters - SW EQ Input Parameters
|
@param[in] PciePort - PCIe Root Port
|
@param[in] OriginalLinkSpeed - Expected speed of the PCIe link
|
@param[in] OriginalLinkWidth - Expected width of the PCIe link
|
@param[out] DeferredPlatformResetRequired - A platform reset is needed after saving Eq data to NVRAM
|
|
@retval EFI_SUCCESS - Link is running at the correct speed/width
|
@retval EFI_UNSUPPORTED - Unable to correct failure due to lack of GPIO PERST# support
|
@retval EFI_INVALID_PARAMETER - Unable to correct failure because the GPIO pin number is invalid
|
@retval EFI_DEVICE_ERROR - Unable to correct link downgrade
|
@retval EFI_TIMEOUT - Link did not successfully retrain
|
**/
|
typedef
|
EFI_STATUS
|
(EFIAPI *PCIE_ENSURE_LINK_IS_HEALTHY)(
|
IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
|
IN PCIE_SWEQ_INPUT_PARAMETERS *InputParameters,
|
IN PCIE_PORT_INFO *PciePort,
|
IN UINT8 OriginalLinkSpeed,
|
IN UINT8 OriginalLinkWidth,
|
OUT BOOLEAN *DeferredPlatformResetRequired
|
);
|
|
///
|
/// PCIe Error Counting Functions
|
///
|
|
/**
|
Open port for monitor
|
|
@param[in] This - Low level function table
|
|
@retval Monitor Port
|
**/
|
typedef
|
UINT32
|
(EFIAPI *PCIE_OPEN_MONITOR)(
|
IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This
|
);
|
|
/**
|
Close port for monitor
|
|
@param[in] This - Low level function table
|
@param[in] MonitorPort - Monitor Port
|
**/
|
typedef
|
VOID
|
(EFIAPI *PCIE_CLOSE_MONITOR)(
|
IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
|
IN UINT32 MonitorPort
|
);
|
|
/**
|
Get Current Error Count
|
|
@param[in] This - Low level function table
|
@param[in] MonitorPort - Monitor Port
|
@param[in] PciePort - PCIe Root Port
|
**/
|
typedef
|
UINT32
|
(EFIAPI *PCIE_GET_ERROR_COUNT)(
|
IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
|
IN UINT32 MonitorPort,
|
IN PCIE_PORT_INFO *PciePort
|
);
|
|
/**
|
Clear Current Error Count for all Root Ports
|
|
@param[in] This - Low level function table
|
@param[in] MonitorPort - Monitor Port
|
**/
|
typedef
|
VOID
|
(EFIAPI *PCIE_CLEAR_ERROR_COUNT)(
|
IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
|
IN UINT32 MonitorPort
|
);
|
|
/**
|
Enable or Disable Polling Compliance Mode
|
|
@param[in] This - Low level function table
|
@param[in] PciePorts - PCIe Root Ports
|
@param[in] PciePortsLength - Length of PciePorts array
|
@param[in] Enable - TRUE to enable, FALSE to disable
|
**/
|
typedef
|
EFI_STATUS
|
(EFIAPI *PCIE_POLLING_COMPLIANCE_MODE)(
|
IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
|
IN PCIE_PORT_INFO *PciePorts,
|
IN UINT8 PciePortsLength,
|
IN BOOLEAN Enable
|
);
|
|
/**
|
Program TxEQs on the endpoint attached to the given root port.
|
|
@param[in] This - Low level function table
|
@param[in] PciePort - PCIe Root Port
|
@param[in] Presets - Array of presets to program per lane
|
must be of sufficient length to program all lanes
|
**/
|
typedef
|
VOID
|
(EFIAPI *PCIE_PROGRAM_PORT_PHASE3_TXEQ)(
|
IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
|
IN PCIE_PORT_INFO *PciePort,
|
IN UINT8 *Presets///[PCIE_MAX_LANE]
|
);
|
|
/**
|
Program the same TxEQ to all lanes on the endpoint attached to the given root port.
|
|
@param[in] This - Low level function table
|
@param[in] PciePort - PCIe Root Port
|
@param[in] Preset - Preset to program
|
**/
|
typedef
|
VOID
|
(EFIAPI *PCIE_PROGRAM_UNIFORM_PORT_PHASE3_TXEQ)(
|
IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
|
IN PCIE_PORT_INFO *PciePort,
|
IN UINT8 Preset
|
);
|
|
/**
|
Runs a Margin Test on the specified root ports. The MarginData parameter must
|
be an array with capacity of PciePortsLength elements or more.
|
|
@param[in] This - Low level function table
|
@param[in] PciePorts - PCIe Root Ports to margin
|
@param[in] PciePortsLength - Length of the PciePorts array
|
@param[in] InputParameters - SW EQ Input Parameters
|
@param[in] MonitorPort - Monitor Port
|
@param[in] MarginTest - Type of Margin Test to Run
|
@param[out] MarginData - Margin Data, must be array of size >= PciePortsLength
|
@param[out] DeferredPlatformResetRequired - A platform reset is needed after saving Eq data to NVRAM
|
|
@retval EFI_SUCCESS - Margin Data Generated Successfully
|
**/
|
typedef
|
EFI_STATUS
|
(EFIAPI *PCIE_RUN_MARGIN_TEST)(
|
IN PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *This,
|
IN PCIE_PORT_INFO *PciePorts,
|
IN UINT8 PciePortsLength,
|
IN PCIE_SWEQ_INPUT_PARAMETERS *InputParameters,
|
IN UINT32 MonitorPort,
|
IN MARGIN_TEST_TYPE MarginTest,
|
OUT PCIE_SWEQ_PORT_OUTPUT *MarginData,
|
OUT BOOLEAN *DeferredPlatformResetRequired
|
);
|
|
struct _PCIE_SI_LOW_LEVEL_FUNCTION_CALLS {
|
VOID *PrivateData;
|
|
///
|
/// Generic Low Level
|
///
|
PCIE_DETECT_ENDPOINT_PRESENCE DetectEndpointPresence;
|
PCIE_GET_PCIE_CAP_OFFSET GetPcieCapOffset;
|
PCIE_DATA_LINK_LAYER_LINK_ACTIVE DataLinkLayerLinkActive;
|
PCIE_GET_SLOT_PRESENCE_DETECT GetSlotPresenceDetect;
|
PCIE_SET_LINK_DISABLE SetLinkDisable;
|
PCIE_RETRAIN_LINK RetrainLink;
|
PCIE_GET_NEGOTIATED_WIDTH GetNegotiatedWidth;
|
PCIE_GET_CURRENT_LINK_SPEED GetCurrentLinkSpeed;
|
PCIE_GET_TARGET_LINK_SPEED GetTargetLinkSpeed;
|
PCIE_SET_TARGET_LINK_SPEED SetTargetLinkSpeed;
|
PCIE_SET_PERST SetPerst;
|
PCIE_ENSURE_LINK_IS_HEALTHY EnsureLinkIsHealthy;
|
|
///
|
/// Silicon Specific Low Level
|
///
|
PCIE_EXISTS PcieExists;
|
PCIE_GET_ROOT_PORTS GetPcieRootPorts;
|
PCIE_PROGRAM_STATIC_GEN3_EQ ProgramStaticGen3Eq;
|
PCIE_SET_GEN3_PHASE2_BYPASS SetPhase2Bypass;
|
PCIE_REPORT_LINK_STATUS ReportPcieLinkStatus;
|
PCIE_WAIT_FOR_L0 WaitForL0;
|
PCIE_RESET_ENDPOINT_PERST ResetEndpointPerst;
|
PCIE_RECOVER_LINK_WIDTH RecoverLinkWidth;
|
PCIE_SET_PCH_GPIO SetPchGpio;
|
PCIE_OPEN_MONITOR OpenMonitor;
|
PCIE_CLOSE_MONITOR CloseMonitor;
|
PCIE_GET_ERROR_COUNT GetErrorCount;
|
PCIE_CLEAR_ERROR_COUNT ClearErrorCount;
|
PCIE_POLLING_COMPLIANCE_MODE PollingComplianceMode;
|
PCIE_PROGRAM_PORT_PHASE3_TXEQ ProgramPortPhase3TxEq;
|
PCIE_PROGRAM_UNIFORM_PORT_PHASE3_TXEQ ProgramUniformPortPhase3TxEq;
|
PCIE_RUN_MARGIN_TEST RunMarginTest;
|
};
|
|
/**
|
Find the Offset to a given Capabilities ID
|
CAPID list:
|
- 0x01 = PCI Power Management Interface
|
- 0x04 = Slot Identification
|
- 0x05 = MSI Capability
|
- 0x10 = PCI Express Capability
|
|
@param[in] Bus - PCI Bus Number
|
@param[in] Device - PCI Device Number
|
@param[in] Function - PCI Function Number
|
@param[in] CapId - CAPID to search for
|
|
@retval 0 - CAPID not found
|
@retval Other - CAPID found, Offset of desired CAPID
|
**/
|
UINT32
|
PcieLibFindCapId (
|
IN UINT8 Bus,
|
IN UINT8 Device,
|
IN UINT8 Function,
|
IN UINT8 CapId
|
);
|
|
/**
|
This function gets the table of generic low level function calls for the PCIe
|
interface. These function calls use PCIe spec defined mechanisms and can be
|
overrided by a silicon specific implementation if needed.
|
|
@param[out] PcieLowLevel - Table of function calls for PCIe
|
|
@retval EFI_SUCCESS - Table of function calls returned successfully
|
**/
|
EFI_STATUS
|
GetGenericPcieLowLevelFunctionCalls (
|
OUT PCIE_SI_LOW_LEVEL_FUNCTION_CALLS *PcieLowLevelFunctionCalls
|
);
|
|
#endif
|
