/** @file
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This file contains the tests for the SecuePCHConfiguration bit
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "HstiSiliconDxe.h"
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/**
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Run tests for SecurePCHConfiguration bit
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**/
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VOID
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CheckSecurePchConfiguration (
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VOID
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)
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{
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EFI_STATUS Status;
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BOOLEAN Result;
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UINT16 PmBase;
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UINT64 Tbar;
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UINT32 TbarL;
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UINT32 TbarH;
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UINT8 Srdl;
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UINT32 GenPmConLock;
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UINT32 PmCfg;
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UINT32 SmiEn;
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UINT8 GenPmCon1;
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UINT16 Tco1Cnt;
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UINT32 Hostc;
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UINT16 Cmd;
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CHAR16 *HstiErrorString;
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UINT32 PchSpiBar0;
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UINT32 PchPwrmBase;
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UINT32 PcrRtc;
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UINT16 TcoBase;
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BOOLEAN ThermalPciMode;
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BOOLEAN ThermalAcpiMode;
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UINT32 ThermalPciBase;
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BOOLEAN ThermalPciModeTbarConfigured;
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ThermalPciMode = FALSE;
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ThermalAcpiMode = FALSE;
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ThermalPciModeTbarConfigured = FALSE;
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if ((mFeatureImplemented[1] & HSTI_BYTE1_SECURE_PCH_CONFIGURATION) == 0) {
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return;
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}
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Result = TRUE;
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PchSpiBar0 = MmioRead32 (MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH,PCI_DEVICE_NUMBER_PCH_SPI,PCI_FUNCTION_NUMBER_PCH_SPI) + R_PCH_SPI_BAR0) & ~B_PCH_SPI_BAR0_MASK;
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PchAcpiBaseGet (&PmBase);
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PchTcoBaseGet (&TcoBase);
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DEBUG ((DEBUG_INFO, " Table 3-10. PCH Security Configuration\n"));
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DEBUG ((DEBUG_INFO, " 1. Thermal Throttling Locks\n"));
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//
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// Check Device VID and DID , if data is not 0xFFFFFFFF, then it's in PCI Mode
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//
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ThermalPciBase = (UINT32) (UINTN) MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH,PCI_DEVICE_NUMBER_PCH_THERMAL,PCI_FUNCTION_NUMBER_PCH_THERMAL);
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if (MmioRead32 (ThermalPciBase + PCI_VENDOR_ID_OFFSET) != 0xFFFFFFFF) {
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ThermalPciMode = TRUE;
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}
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if (ThermalPciMode) {
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TbarL = MmioRead32 (ThermalPciBase + R_PCH_THERMAL_TBAR);
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TbarH = MmioRead32 (ThermalPciBase + R_PCH_THERMAL_TBARH);
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TbarL = TbarL & B_PCH_THERMAL_TBAR_MASK;
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Tbar = ((UINT64) TbarH << 32) | TbarL;
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//
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// Check if Tbar is initialized. If Tbar is 0 , then Tbar is not initialized , Use PCH_THERMAL_BASE_ADDRESS for Tbar
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// and write TbarL and TbarH back to register
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//
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if (Tbar == 0) {
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Tbar = (UINT64) PCH_THERMAL_BASE_ADDRESS;
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TbarL = (UINT32) Tbar;
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TbarH = (UINT32) ((UINT64) Tbar >> 32);
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MmioWrite32 (ThermalPciBase + R_PCH_THERMAL_TBAR, TbarL);
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MmioWrite32 (ThermalPciBase + R_PCH_THERMAL_TBARH, TbarH);
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ThermalPciModeTbarConfigured = TRUE;
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}
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//
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// Make sure MSE bit is enabled before trying to access Tbar MMIO
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//
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Cmd = MmioRead16 (ThermalPciBase + PCI_COMMAND_OFFSET);
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MmioWrite16 (ThermalPciBase + PCI_COMMAND_OFFSET, Cmd | EFI_PCI_COMMAND_MEMORY_SPACE);
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//
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// Not in Pci Mode
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//
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} else {
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Tbar = (UINT64) PCH_THERMAL_BASE_ADDRESS;
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//
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// This is to probe the Thermal in ACPI mode.
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// If Thermal is in ACPI mode, the TBAR must be PCH_THERMAL_BASE_ADDRESS and the offset 0 (TEMP) must return valid temperature.
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//
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if (MmioRead16 ((UINT32)Tbar + 0x00) != 0xFFFF) {
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ThermalAcpiMode = TRUE;
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}
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}
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if (ThermalPciMode || ThermalAcpiMode) {
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if ((MmioRead32 (Tbar + R_PCH_TBAR_TCFD) & B_PCH_TBAR_TCFD_TCD) == 0) {
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if (((MmioRead8 (Tbar + R_PCH_TBAR_TSC) & B_PCH_TBAR_TSC_PLD) == 0) ||
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((MmioRead8 (Tbar + R_PCH_TBAR_TSEL) & B_PCH_TBAR_TSEL_PLD) == 0) ||
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((MmioRead8 (Tbar + R_PCH_TBAR_TSMIC) & B_PCH_TBAR_TSMIC_PLD) == 0) ||
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((MmioRead32 (Tbar + R_PCH_TBAR_TL) & B_PCH_TBAR_TL_LOCK) == 0) ||
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((MmioRead8 (Tbar + R_PCH_TBAR_PHLC) & BIT0) == 0)) {
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HstiErrorString = BuildHstiErrorString (HSTI_BYTE1_SECURE_PCH_CONFIGURATION_ERROR_CODE_1 ,HSTI_PCH_SECURITY_CONFIGURATION, HSTI_BYTE1_SECURE_PCH_CONFIGURATION_ERROR_STRING_1);
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Status = HstiLibAppendErrorString (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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HstiErrorString
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);
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ASSERT_EFI_ERROR (Status);
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Result = FALSE;
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FreePool (HstiErrorString);
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}
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}
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}
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if (ThermalPciMode) {
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//
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// Restore CMD register
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//
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MmioWrite16 ((ThermalPciBase + PCI_COMMAND_OFFSET), Cmd);
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//
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// If Tbar had been configured because of initialization. Restore Tbar ,TbarH and TbarL
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//
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if (ThermalPciModeTbarConfigured) {
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MmioWrite32 (ThermalPciBase + R_PCH_THERMAL_TBAR, 0);
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MmioWrite32 (ThermalPciBase + R_PCH_THERMAL_TBARH, 0);
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}
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}
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DEBUG ((DEBUG_INFO, " 2. Set Strap Lock\n"));
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Srdl = MmioRead8 (PchSpiBar0 + R_PCH_SPI_SSML);
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if ((Srdl & B_PCH_SPI_SSML_SSL) == 0) {
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DEBUG ((DEBUG_INFO, "Set Strap Lock %x\n",Srdl));
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HstiErrorString = BuildHstiErrorString (HSTI_BYTE1_SECURE_PCH_CONFIGURATION_ERROR_CODE_2 ,HSTI_PCH_SECURITY_CONFIGURATION, HSTI_BYTE1_SECURE_PCH_CONFIGURATION_ERROR_STRING_2);
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Status = HstiLibAppendErrorString (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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HstiErrorString
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);
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ASSERT_EFI_ERROR (Status);
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Result = FALSE;
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FreePool (HstiErrorString);
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}
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DEBUG ((DEBUG_INFO, " 3. ACPI Base Lock\n"));
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GenPmConLock = MmioRead32 (MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH,PCI_DEVICE_NUMBER_PCH_PMC,PCI_FUNCTION_NUMBER_PCH_PMC) + R_PCH_PMC_GEN_PMCON_B);
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if ((GenPmConLock & B_PCH_PMC_GEN_PMCON_B_ACPI_BASE_LOCK) == 0) {
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HstiErrorString = BuildHstiErrorString (HSTI_BYTE1_SECURE_PCH_CONFIGURATION_ERROR_CODE_2 ,HSTI_PCH_SECURITY_CONFIGURATION, HSTI_BYTE1_SECURE_PCH_CONFIGURATION_ERROR_STRING_2);
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Status = HstiLibAppendErrorString (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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HstiErrorString
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);
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ASSERT_EFI_ERROR (Status);
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Result = FALSE;
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FreePool (HstiErrorString);
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}
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DEBUG ((DEBUG_INFO, " 4. PM_CFG\n"));
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PchPwrmBaseGet (&PchPwrmBase);
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PmCfg = MmioRead32 (PchPwrmBase + R_PCH_PWRM_CFG);
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if (((PmCfg & BIT22) == 0) ||
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((PmCfg & BIT27) == 0)) {
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HstiErrorString = BuildHstiErrorString (HSTI_BYTE1_SECURE_PCH_CONFIGURATION_ERROR_CODE_3 ,HSTI_PCH_SECURITY_CONFIGURATION, HSTI_BYTE1_SECURE_PCH_CONFIGURATION_ERROR_STRING_3);
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Status = HstiLibAppendErrorString (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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HstiErrorString
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);
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ASSERT_EFI_ERROR (Status);
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Result = FALSE;
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FreePool (HstiErrorString);
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}
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DEBUG ((DEBUG_INFO, " 5. SMI Enable\n"));
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SmiEn = IoRead32 (PmBase + R_PCH_SMI_EN);
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if ((SmiEn & B_PCH_SMI_EN_GBL_SMI) == 0x0) {
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HstiErrorString = BuildHstiErrorString (HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_CODE_D ,HSTI_PCH_SECURITY_CONFIGURATION, HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_STRING_D);
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Status = HstiLibAppendErrorString (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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HstiErrorString
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);
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ASSERT_EFI_ERROR (Status);
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Result = FALSE;
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FreePool (HstiErrorString);
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}
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DEBUG ((DEBUG_INFO, " 6. SMI Lock\n"));
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GenPmCon1 = MmioRead8 (MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH,PCI_DEVICE_NUMBER_PCH_PMC,PCI_FUNCTION_NUMBER_PCH_PMC) + R_PCH_PMC_GEN_PMCON_A);
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if ((GenPmCon1 & B_PCH_PMC_GEN_PMCON_A_SMI_LOCK) == 0x0) {
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HstiErrorString = BuildHstiErrorString (HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_CODE_D ,HSTI_PCH_SECURITY_CONFIGURATION, HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_STRING_D);
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Status = HstiLibAppendErrorString (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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HstiErrorString
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);
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ASSERT_EFI_ERROR (Status);
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Result = FALSE;
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FreePool (HstiErrorString);
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}
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DEBUG ((DEBUG_INFO, " 7. TCO SMI Lock\n"));
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Tco1Cnt = IoRead16 (TcoBase + R_PCH_TCO1_CNT);
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if ((Tco1Cnt & B_PCH_TCO_CNT_LOCK) == 0x0) {
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DEBUG ((DEBUG_INFO, "TCO SMI Lock %x\n",(Tco1Cnt & B_PCH_TCO_CNT_LOCK)));
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HstiErrorString = BuildHstiErrorString (HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_CODE_E ,HSTI_PCH_SECURITY_CONFIGURATION, HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_STRING_E);
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Status = HstiLibAppendErrorString (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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HstiErrorString
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);
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ASSERT_EFI_ERROR (Status);
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Result = FALSE;
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FreePool (HstiErrorString);
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}
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DEBUG ((DEBUG_INFO, " 8. RTC Bios Interface Lock\n"));
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PcrRtc = MmioRead32 (PCH_PCR_ADDRESS (PID_RTC,R_PCH_PCR_RTC_CONF));
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if ((PcrRtc & BIT31) == 0x0) {
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DEBUG ((DEBUG_INFO, "Rtc BILD %x\n",(PcrRtc & BIT31)));
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HstiErrorString = BuildHstiErrorString (HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_CODE_4 ,HSTI_PCH_SECURITY_CONFIGURATION, HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_STRING_4);
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Status = HstiLibAppendErrorString (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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HstiErrorString
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);
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ASSERT_EFI_ERROR (Status);
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Result = FALSE;
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FreePool (HstiErrorString);
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}
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DEBUG ((DEBUG_INFO, " Table 7-7. SPD Configuration and Write Protection\n"));
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Hostc = MmioRead32 (MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH,PCI_DEVICE_NUMBER_PCH_SMBUS,PCI_FUNCTION_NUMBER_PCH_SMBUS) + R_PCH_SMBUS_HOSTC);
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if ((Hostc & B_PCH_SMBUS_HOSTC_SPDWD) == 0) {
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HstiErrorString = BuildHstiErrorString (HSTI_BYTE1_SECURE_MEMORY_MAP_CONFIGURATION_ERROR_CODE_4 ,HSTI_PROCESSOR_SPD_SECURITY_CONFIGURATION, HSTI_BYTE1_SECURE_MEMORY_MAP_CONFIGURATION_ERROR_STRING_4);
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Status = HstiLibAppendErrorString (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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HstiErrorString
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);
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ASSERT_EFI_ERROR (Status);
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Result = FALSE;
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FreePool (HstiErrorString);
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}
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//
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// ALL PASS
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//
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if (Result) {
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Status = HstiLibSetFeaturesVerified (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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1,
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HSTI_BYTE1_SECURE_PCH_CONFIGURATION
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);
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ASSERT_EFI_ERROR (Status);
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}
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return;
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}
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