/** @file
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This file contains the tests for the SecureCPUConfiguration bit
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "HstiSiliconDxe.h"
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/**
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Run tests for SecureCPUConfiguration bit
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**/
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VOID
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CheckSecureCpuConfiguration (
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VOID
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)
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{
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EFI_STATUS Status;
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BOOLEAN Result;
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UINTN CpuNumber;
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UINTN CpuIndex;
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CPUID_VERSION_INFO_ECX Ecx;
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UINT8 SramC;
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UINT32 TsegMB;
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UINT32 Bgsm;
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UINT64 SmrrBase;
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UINT64 SmrrMask;
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UINT64 MasterSmrrBase;
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UINT64 MasterSmrrMask;
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CHAR16 *HstiErrorString;
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UINT64 SmmFeatureControl;
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MSR_IA32_FEATURE_CONTROL_REGISTER Ia32FeatureControlMsr;
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MSR_IA32_MTRRCAP_REGISTER MtrrCapMsr;
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if ((mFeatureImplemented[0] & HSTI_BYTE0_SECURE_CPU_CONFIGURATION) == 0) {
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return;
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}
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Result = TRUE;
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DEBUG ((DEBUG_INFO, " Table 3-1. CPU Security Configuration\n"));
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CpuNumber = GetCpuNumber ();
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for (CpuIndex = 0; CpuIndex < CpuNumber; CpuIndex++) {
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DEBUG ((DEBUG_INFO, " [CPU - 0x%x]\n", CpuIndex));
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DEBUG ((DEBUG_INFO, " 1. Microcode Update Revision\n"));
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if ((ProcessorReadMsr64 (CpuIndex, MSR_IA32_BIOS_SIGN_ID) & 0xFFFFFFFF00000000) == 0) {
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HstiErrorString = BuildHstiErrorString (HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_1 ,HSTI_CPU_SECURITY_CONFIGURATION, HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_1);
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Status = HstiLibAppendErrorString (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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HstiErrorString
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);
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ASSERT_EFI_ERROR (Status);
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Result = FALSE;
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FreePool (HstiErrorString);
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}
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DEBUG ((DEBUG_INFO, " 2. Sample Part \n"));
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if ((ProcessorReadMsr64 (CpuIndex, MSR_PLATFORM_INFO) & BIT27) != 0) {
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DEBUG ((DEBUG_INFO, "Fail: This is a sample part\n"));
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HstiErrorString = BuildHstiErrorString (HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_2 ,HSTI_CPU_SECURITY_CONFIGURATION, HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_2);
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Status = HstiLibAppendErrorString (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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HstiErrorString
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);
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ASSERT_EFI_ERROR (Status);
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Result = FALSE;
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FreePool (HstiErrorString);
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}
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DEBUG ((DEBUG_INFO, " 3. IA32_FEATURE_CONTROL MSR Lock\n"));
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Ia32FeatureControlMsr.Uint64 = ProcessorReadMsr64 (CpuIndex, MSR_IA32_FEATURE_CONTROL);
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if (Ia32FeatureControlMsr.Bits.Lock == 0) {
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DEBUG ((DEBUG_INFO, "Fail: This is a sample part\n"));
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HstiErrorString = BuildHstiErrorString (HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_3 ,HSTI_CPU_SECURITY_CONFIGURATION, HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_3);
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Status = HstiLibAppendErrorString (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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HstiErrorString
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);
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ASSERT_EFI_ERROR (Status);
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Result = FALSE;
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FreePool (HstiErrorString);
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}
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DEBUG ((DEBUG_INFO, " 4. SMM_FEATURE_CONTROL MSR Lock\n"));
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SmmFeatureControl = ProcessorReadMsr64 (CpuIndex, MSR_SMM_FEATURE_CONTROL);
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DEBUG ((DEBUG_INFO, " 4. SMM_CODE_CHK_EN TEST\n"));
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if ((SmmFeatureControl & B_SMM_CODE_CHK_EN) == 0) {
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DEBUG ((DEBUG_INFO, "Fail: SMM Code Fetch outside SMRAM dectect feature disabled\n"));
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HstiErrorString = BuildHstiErrorString(HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_4 ,HSTI_CPU_SECURITY_CONFIGURATION, HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_B);
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Status = HstiLibAppendErrorString(
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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HstiErrorString
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);
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ASSERT_EFI_ERROR (Status);
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Result = FALSE;
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FreePool(HstiErrorString);
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}
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DEBUG ((DEBUG_INFO, " SMM_FEATURE_CONTROL MSR Lock\n"));
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if ((SmmFeatureControl & B_SMM_FEATURE_CONTROL_LOCK) == 0) {
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DEBUG ((DEBUG_INFO, "Fail: Smm feature control msr not locked\n"));
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HstiErrorString = BuildHstiErrorString (HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_4 ,HSTI_CPU_SECURITY_CONFIGURATION, HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_4);
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Status = HstiLibAppendErrorString (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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HstiErrorString
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);
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ASSERT_EFI_ERROR (Status);
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Result = FALSE;
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FreePool (HstiErrorString);
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}
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DEBUG ((DEBUG_INFO, " 5. FEATURE_CONFIG MSR Lock\n"));
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ProcessorCpuid (CpuIndex, CPUID_VERSION_INFO, NULL, NULL, &Ecx.Uint32, NULL);
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if (Ecx.Bits.AESNI == 1) {
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if ((ProcessorReadMsr64 (CpuIndex, MSR_IA32_FEATURE_CONFIG) & B_IA32_FEATURE_CONFIG_LOCK) == 0) {
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DEBUG ((DEBUG_INFO, "Fail: Feature control msr not locked\n"));
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HstiErrorString = BuildHstiErrorString (HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_5 ,HSTI_CPU_SECURITY_CONFIGURATION, HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_5);
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Status = HstiLibAppendErrorString (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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HstiErrorString
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);
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ASSERT_EFI_ERROR (Status);
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Result = FALSE;
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FreePool (HstiErrorString);
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}
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}
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}
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DEBUG ((DEBUG_INFO, " Table 7-4. SMM Security Configuration\n"));
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DEBUG ((DEBUG_INFO, " 1. SMRAMC\n"));
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SramC = MmioRead8 (MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH,SA_MC_DEV,SA_MC_FUN) + R_SA_SMRAMC);
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if ((SramC & B_SA_SMRAMC_D_LCK_MASK) == 0) {
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DEBUG ((DEBUG_INFO, "Fail: SMRAMC not locked\n"));
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HstiErrorString = BuildHstiErrorString (HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_8 ,HSTI_CPU_SECURITY_CONFIGURATION, HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_8);
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Status = HstiLibAppendErrorString (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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HstiErrorString
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);
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ASSERT_EFI_ERROR (Status);
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Result = FALSE;
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FreePool (HstiErrorString);
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}
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DEBUG ((DEBUG_INFO, " 2. TSEGMB\n"));
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TsegMB = MmioRead32 (MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH,SA_MC_DEV,SA_MC_FUN) + R_SA_TSEGMB);
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if ((TsegMB & B_SA_TSEGMB_LOCK_MASK) == 0) {
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DEBUG ((DEBUG_INFO, "Fail: TSEGMB not locked\n"));
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HstiErrorString = BuildHstiErrorString (HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_8 ,HSTI_CPU_SECURITY_CONFIGURATION, HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_8);
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Status = HstiLibAppendErrorString (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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HstiErrorString
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);
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ASSERT_EFI_ERROR (Status);
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Result = FALSE;
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FreePool (HstiErrorString);
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}
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DEBUG ((DEBUG_INFO, " 3. TSEGMB Alignment\n"));
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if (((TsegMB & B_SA_TSEGMB_TSEGMB_MASK) & (LShiftU64 (1,20) - 1)) != 0) {
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DEBUG ((DEBUG_INFO, "Fail: TSEGMB not size aligned, TSEG size: 0x%x\n",(LShiftU64 (1,20) - 1)));
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HstiErrorString = BuildHstiErrorString (HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_9 ,HSTI_CPU_SECURITY_CONFIGURATION, HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_9);
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Status = HstiLibAppendErrorString (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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HstiErrorString
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);
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ASSERT_EFI_ERROR (Status);
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Result = FALSE;
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FreePool (HstiErrorString);
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}
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MasterSmrrBase = 0;
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MasterSmrrMask = 0;
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for (CpuIndex = 0; CpuIndex < CpuNumber; CpuIndex++) {
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DEBUG ((DEBUG_INFO, " [CPU - 0x%x]\n", CpuIndex));
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DEBUG ((DEBUG_INFO, " 4. SMRR1 are supported\n"));
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MtrrCapMsr.Uint64 = ProcessorReadMsr64 (CpuIndex, MSR_IA32_MTRRCAP);
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if (MtrrCapMsr.Bits.SMRR == 0) {
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DEBUG ((DEBUG_INFO, "Fail: SMRR1 not supported\n"));
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HstiErrorString = BuildHstiErrorString (HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_A ,HSTI_CPU_SECURITY_CONFIGURATION, HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_A);
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Status = HstiLibAppendErrorString (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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HstiErrorString
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);
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ASSERT_EFI_ERROR (Status);
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Result = FALSE;
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FreePool (HstiErrorString);
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} else {
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DEBUG ((DEBUG_INFO, " 5. SMRR1 programmed consistently on all cores\n"));
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SmrrBase = ProcessorReadMsr64 (CpuIndex, MSR_IA32_SMRR_PHYSBASE);
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SmrrMask = ProcessorReadMsr64 (CpuIndex, MSR_IA32_SMRR_PHYSMASK);
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if (CpuIndex == 0) {
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MasterSmrrBase = SmrrBase;
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MasterSmrrMask = SmrrMask;
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} else {
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if ((SmrrBase != MasterSmrrBase) || (SmrrMask != MasterSmrrMask)) {
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DEBUG ((DEBUG_INFO, "Fail: SMRR1 not programmed consistently across all cores\n"));
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HstiErrorString = BuildHstiErrorString (HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_A ,HSTI_CPU_SECURITY_CONFIGURATION, HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_A);
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Status = HstiLibAppendErrorString (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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HstiErrorString
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);
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ASSERT_EFI_ERROR (Status);
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Result = FALSE;
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FreePool (HstiErrorString);
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}
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}
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DEBUG ((DEBUG_INFO, " 6. SMRR1 enabled/correct\n"));
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if (((SmrrMask & BIT11) == 0x0) ||
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((SmrrMask & BIT9) != 0x0) ||
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((SmrrBase & 0x7) != 0x6)) {
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DEBUG ((DEBUG_INFO, "Fail: SMRR1 not enabled/correct\n"));
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HstiErrorString = BuildHstiErrorString (HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_A ,HSTI_CPU_SECURITY_CONFIGURATION, HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_A);
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Status = HstiLibAppendErrorString (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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HstiErrorString
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);
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ASSERT_EFI_ERROR (Status);
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Result = FALSE;
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FreePool (HstiErrorString);
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}
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DEBUG ((DEBUG_INFO, " 7. SMRR1 and TSEGMB match\n"));
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DEBUG ((DEBUG_INFO, "SMRR: 0x%08x - 0x%08x\n", SmrrBase & (SmrrMask & 0xFFFFF000), (UINT32) (~(SmrrMask & 0xFFFFF000) + 1)));
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DEBUG ((DEBUG_INFO, "TSEGMB: 0x%08x\n", TsegMB & B_SA_TSEGMB_TSEGMB_MASK));
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if ((SmrrBase & (SmrrMask & 0xFFFFF000)) != (TsegMB & B_SA_TSEGMB_TSEGMB_MASK)) {
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DEBUG ((DEBUG_INFO, "Fail: SMRR1 != TSEGMB\n"));
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HstiErrorString = BuildHstiErrorString (HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_A ,HSTI_CPU_SECURITY_CONFIGURATION, HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_A);
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Status = HstiLibAppendErrorString (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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HstiErrorString
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);
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ASSERT_EFI_ERROR (Status);
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Result = FALSE;
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FreePool (HstiErrorString);
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}
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DEBUG ((DEBUG_INFO, " 8. SMRR1 size\n"));
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Bgsm = MmioRead32 (MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH,SA_MC_DEV,SA_MC_FUN) + R_SA_BGSM);
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if ((UINT32) (~(SmrrMask & 0xFFFFF000) + 1) !=
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((Bgsm & B_SA_BGSM_BGSM_MASK) - (TsegMB & B_SA_TSEGMB_TSEGMB_MASK))) {
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DEBUG ((DEBUG_INFO, "Fail: SMRR1 size != BGSM-TSEGMB\n"));
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HstiErrorString = BuildHstiErrorString (HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_A ,HSTI_CPU_SECURITY_CONFIGURATION, HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_A);
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Status = HstiLibAppendErrorString (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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HstiErrorString
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);
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ASSERT_EFI_ERROR (Status);
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Result = FALSE;
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FreePool (HstiErrorString);
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}
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DEBUG ((DEBUG_INFO, " 9. SMRR1 work\n"));
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if (MmioRead32 (SmrrBase & SmrrMask) != 0xFFFFFFFF) {
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DEBUG ((DEBUG_INFO, "Fail: SMRR1 not working, read succeeded\n"));
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HstiErrorString = BuildHstiErrorString (HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_A ,HSTI_CPU_SECURITY_CONFIGURATION, HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_A);
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Status = HstiLibAppendErrorString (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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HstiErrorString
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);
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ASSERT_EFI_ERROR (Status);
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Result = FALSE;
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FreePool (HstiErrorString);
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}
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}
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}
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//
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// ALL PASS
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//
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if (Result) {
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Status = HstiLibSetFeaturesVerified (
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PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
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NULL,
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0,
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HSTI_BYTE0_SECURE_CPU_CONFIGURATION
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);
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ASSERT_EFI_ERROR (Status);
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}
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return;
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}
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