/** @file
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CPU Common Lib implementation.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Uefi.h>
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#include <Library/BaseLib.h>
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#include <Library/CpuLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/PciLib.h>
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#include <Library/TimerLib.h>
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#include <Library/CpuPlatformLib.h>
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#include <Library/CpuMailboxLib.h>
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#include <Register/Cpuid.h>
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#include <Register/Msr.h>
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#include <CpuAccess.h>
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#include <Library/CpuCommonLib.h>
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#define INTERRUPT_VECTOR_NUMBER 256
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#define END_OF_TIMETABLE 0x3FF
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/**
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Set up flags in CR4 for XMM instruction enabling
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**/
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VOID
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EFIAPI
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XmmInit (
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VOID
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)
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{
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EFI_CPUID_REGISTER Cpuid;
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UINTN Cr0;
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UINTN Cr4;
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///
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/// Read the CPUID information
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///
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AsmCpuid (CPUID_VERSION_INFO, &Cpuid.RegEax, &Cpuid.RegEbx, &Cpuid.RegEcx, &Cpuid.RegEdx);
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///
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/// Check whether SSE2 is supported
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///
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if (Cpuid.RegEdx & BIT26) {
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///
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/// Enable XMM
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///
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Cr0 = AsmReadCr0 ();
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Cr0 |= BIT1;
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AsmWriteCr0 (Cr0);
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Cr4 = AsmReadCr4 ();
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Cr4 |= (UINTN) (BIT9 | BIT10);
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AsmWriteCr4 (Cr4);
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}
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}
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/**
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Enable "Machine Check Enable" bit in Cr4
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**/
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VOID
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EFIAPI
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EnableMce (
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VOID
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)
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{
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UINTN Cr4;
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///
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/// Enable MCE
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///
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Cr4 = AsmReadCr4 ();
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Cr4 |= BIT6;
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AsmWriteCr4 (Cr4);
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}
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/**
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Mtrr Synch Up Entry
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**/
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UINTN
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EFIAPI
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MpMtrrSynchUpEntry (
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VOID
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)
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{
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EFI_CPUID_REGISTER Cpuid;
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UINT64 MsrData;
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UINTN Cr0;
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UINTN Cr4;
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///
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/// Read the CPUID and MSR 1Bh information
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///
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AsmCpuid (CPUID_VERSION_INFO, &Cpuid.RegEax, &Cpuid.RegEbx, &Cpuid.RegEcx, &Cpuid.RegEdx);
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MsrData = AsmReadMsr64 (MSR_IA32_APIC_BASE);
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///
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/// Set CD(Bit30) bit and clear NW(Bit29) bit of CR0 followed by a WBINVD.
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///
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if (!(Cpuid.RegEdx & BIT24) || (MsrData & BIT8)) {
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AsmDisableCache ();
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} else {
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///
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/// We could bypass the wbinvd by
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/// checking MSR 1Bh(MSR_IA32_APIC_BASE) Bit8 (1 = BSP, 0 = AP) to see if we're the BSP?
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/// and checking CPUID if the processor support self-snooping.
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///
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Cr0 = AsmReadCr0 ();
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Cr0 &= (UINTN) ~BIT29;
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Cr0 |= BIT30;
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AsmWriteCr0 (Cr0);
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}
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///
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/// Clear PGE flag Bit 7
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///
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Cr4 = AsmReadCr4 ();
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Cr4 &= (UINTN) ~BIT7;
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AsmWriteCr4 (Cr4);
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///
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/// Flush all TLBs
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///
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CpuFlushTlb ();
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return Cr4;
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}
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/**
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Mtrr Synch Up Exit
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**/
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VOID
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EFIAPI
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MpMtrrSynchUpExit (
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UINTN Cr4
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)
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{
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UINTN Cr0;
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///
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/// Flush all TLBs the second time
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///
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CpuFlushTlb ();
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///
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/// Clear both the CD and NW bits of CR0.
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///
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Cr0 = AsmReadCr0 ();
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Cr0 &= (UINTN) ~(BIT29 | BIT30);
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AsmWriteCr0 (Cr0);
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///
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/// Set PGE Flag in CR4 if set
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///
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AsmWriteCr4 (Cr4);
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}
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/**
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This procedure sends an IPI to the designated processor in
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the requested delivery mode with the requested vector.
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@param[in] ApicID - APIC ID of processor.
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@param[in] VectorNumber - Vector number.
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@param[in] DeliveryMode - I/O APIC Interrupt Deliver Modes
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@retval EFI_INVALID_PARAMETER - Input paramters were not correct.
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@retval EFI_NOT_READY - There was a pending interrupt
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@retval EFI_SUCCESS - Interrupt sent successfully
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**/
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EFI_STATUS
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EFIAPI
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CpuSendIpi (
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IN UINT32 ApicID,
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IN UINTN VectorNumber,
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IN UINTN DeliveryMode
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)
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{
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MSR_IA32_APIC_BASE_REGISTER Msr;
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EFI_PHYSICAL_ADDRESS ApicBase;
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UINT32 IcrLow;
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UINT32 IcrHigh;
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BOOLEAN XapicEnabled;
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UINT32 TriggerMode;
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///
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/// Check for valid input parameters.
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///
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if (VectorNumber >= INTERRUPT_VECTOR_NUMBER) {
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return EFI_INVALID_PARAMETER;
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}
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if (DeliveryMode >= DELIVERY_MODE_MAX) {
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return EFI_INVALID_PARAMETER;
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}
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///
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/// Fix the vector number for special interrupts like SMI and INIT.
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///
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if (DeliveryMode == DELIVERY_MODE_SMI || DeliveryMode == DELIVERY_MODE_INIT) {
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VectorNumber = 0x0;
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}
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///
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/// Initialze ICR high dword, since P6 family processor needs
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/// the destination field to be 0x0F when it is a broadcast
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///
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IcrHigh = 0x0f000000;
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IcrLow = (UINT32) (VectorNumber | (LShiftU64 (DeliveryMode, 8)));
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TriggerMode = TRIGGER_MODE_EDGE;
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///
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/// Interrupt trigger mode
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///
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if (TriggerMode == TRIGGER_MODE_LEVEL) {
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IcrLow |= 0x8000;
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}
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///
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/// Interrupt pin polarity
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///
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IcrLow |= 0x4000;
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///
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/// xAPIC Enabled
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///
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Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
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XapicEnabled = (BOOLEAN) ((Msr.Bits.EXTD == 1) && (Msr.Bits.EN == 1));
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if (XapicEnabled) {
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IcrHigh = (UINT32) ApicID;
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} else {
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IcrHigh = (UINT32) LShiftU64 (ApicID, 24);
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}
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ApicBase = Msr.Uint64 & 0xffffff000;
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/* If Extended XAPIC Mode is enabled,
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legacy xAPIC is no longer working.
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So, previous MMIO offset must be transferred to MSR offset R/W.
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----------------------------------------------------------------
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MMIO Offset MSR Offset Register Name
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----------------------------------------------------------------
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300h-310h 830h Interrupt Command Register [63:0]
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831h [Reserved]
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----------------------------------------------------------------
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*/
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///
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/// To write APIC register by MSR or MMIO
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///
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if (XapicEnabled) {
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AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, (((UINT64) LShiftU64 (IcrHigh, 32)) | (UINT64) IcrLow));
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} else {
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*(volatile UINT32 *) (UINTN) (ApicBase + APIC_REGISTER_ICR_HIGH_OFFSET) = (UINT32) IcrHigh;
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*(volatile UINT32 *) (UINTN) (ApicBase + APIC_REGISTER_ICR_LOW_OFFSET) = (UINT32) IcrLow;
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}
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MicroSecondDelay (10);
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///
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/// To get APIC register from MSR or MMIO
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///
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if (XapicEnabled) {
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IcrLow = (UINT32) AsmReadMsr64 (MSR_IA32_X2APIC_ICR);
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} else {
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IcrLow = (UINT32) *(volatile UINT32 *) (UINTN) (ApicBase + APIC_REGISTER_ICR_LOW_OFFSET);
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}
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if (IcrLow & BIT12) {
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return EFI_NOT_READY;
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}
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MicroSecondDelay (100);
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return EFI_SUCCESS;
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}
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/**
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Get APIC ID of processor
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@retval APIC ID of processor
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**/
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UINT32
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GetCpuApicId (
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VOID
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)
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{
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EFI_CPUID_REGISTER CpuidRegisters;
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AsmCpuid (
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CPUID_VERSION_INFO,
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&CpuidRegisters.RegEax,
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&CpuidRegisters.RegEbx,
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&CpuidRegisters.RegEcx,
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&CpuidRegisters.RegEdx
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);
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return (UINT32) (CpuidRegisters.RegEbx >> 24);
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}
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/**
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Programs XAPIC registers.
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@param[in] Bsp - Is this BSP?
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**/
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VOID
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ProgramXApic (
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BOOLEAN Bsp
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)
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{
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UINT64 ApicBaseReg;
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EFI_PHYSICAL_ADDRESS ApicBase;
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volatile UINT32 *EntryAddress;
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UINT32 EntryValue;
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ApicBaseReg = AsmReadMsr64 (MSR_IA32_APIC_BASE);
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ApicBase = ApicBaseReg & 0xffffff000ULL;
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///
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/// Program the spurious vector entry
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///
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EntryAddress = (UINT32 *) (UINTN) (ApicBase + APIC_REGISTER_SPURIOUS_VECTOR_OFFSET);
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EntryValue = *EntryAddress;
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EntryValue &= 0xFFFFFD0F;
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EntryValue |= 0x10F;
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*EntryAddress = EntryValue;
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///
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/// Program the LINT1 vector entry as extINT
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///
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EntryAddress = (UINT32 *) (UINTN) (ApicBase + APIC_REGISTER_LINT0_VECTOR_OFFSET);
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EntryValue = *EntryAddress;
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if (Bsp) {
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EntryValue &= 0xFFFE00FF;
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EntryValue |= 0x700;
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} else {
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EntryValue |= 0x10000;
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}
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*EntryAddress = EntryValue;
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///
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/// Program the LINT1 vector entry as NMI
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///
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EntryAddress = (UINT32 *) (UINTN) (ApicBase + APIC_REGISTER_LINT1_VECTOR_OFFSET);
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EntryValue = *EntryAddress;
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EntryValue &= 0xFFFE00FF;
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if (Bsp) {
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EntryValue |= 0x400;
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} else {
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EntryValue |= 0x10400;
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}
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*EntryAddress = EntryValue;
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}
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/**
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This function is to disable BIOS Write Protect in SMM phase.
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**/
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VOID
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EFIAPI
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CpuSmmDisableBiosWriteProtect (
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VOID
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)
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{
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UINT32 Data32;
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///
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/// Read memory location FED30880h OR with 00000001h, place the result in EAX,
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/// and write data to lower 32 bits of MSR 1FEh (sample code available)
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///
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Data32 = MmioRead32 ((UINTN) (0xFED30880)) | (UINT32) (BIT0);
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AsmWriteMsr32 (0x000001FE, Data32);
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}
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/**
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This function is to enable BIOS Write Protect in SMM phase.
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**/
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VOID
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EFIAPI
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CpuSmmEnableBiosWriteProtect (
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VOID
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)
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{
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UINT32 Data32;
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///
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/// Read memory location FED30880h AND with FFFFFFFEh, place the result in EAX,
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/// and write data to lower 32 bits of MSR 1FEh (sample code available)
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///
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Data32 = MmioRead32 ((UINTN) (0xFED30880)) & (UINT32) (~BIT0);
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AsmWriteMsr32 (0x000001FE, Data32);
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}
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/**
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This function returns the maximum number of cores supported in this physical processor package.
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@retval Maximum number of supported cores in the package.
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**/
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UINT8
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GetMaxSupportedCoreCount (
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VOID
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)
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{
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EFI_CPUID_REGISTER Cpuid;
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AsmCpuidEx (
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4,
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0,
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&Cpuid.RegEax,
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NULL,
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NULL,
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NULL
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);
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return (UINT8) (RShiftU64 (Cpuid.RegEax, 26) & 0x3f) + 1;
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}
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/**
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This function returns the actual factory-configured number of threads per core,
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and actual factory-configured number of cores in this physical processor package.
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@param[out] *ThreadsPerCore - variable that will store Maximum enabled threads per core
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@param[out] *NumberOfCores - variable that will store Maximum enabled cores per die
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**/
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VOID
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GetSupportedCount (
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OUT UINT16 *ThreadsPerCore, OPTIONAL
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OUT UINT16 *NumberOfCores OPTIONAL
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)
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{
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EFI_CPUID_REGISTER CpuidRegs;
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UINT16 Threads;
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AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, NULL, &CpuidRegs.RegEbx, NULL, NULL);
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Threads = (UINT16) CpuidRegs.RegEbx;
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if (ThreadsPerCore != NULL) {
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*ThreadsPerCore = Threads;
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}
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if (NumberOfCores != NULL) {
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AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 1, NULL, &CpuidRegs.RegEbx, NULL, NULL);
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*NumberOfCores = (UINT16) (CpuidRegs.RegEbx / Threads);
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}
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}
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/**
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Check to see if the executing thread is BSP
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@retval TRUE Executing thread is BSP
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@retval FALSE Executing thread is AP
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**/
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BOOLEAN
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IsBsp (
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VOID
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)
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{
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MSR_IA32_APIC_BASE_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
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return (BOOLEAN) (Msr.Bits.BSP == 1);
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}
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BOOLEAN
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IsPrmrrAlreadySet (
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VOID
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)
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{
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return FALSE;
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}
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/**
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Check if this is non-core processor - HT AP thread
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@retval TRUE if this is HT AP thread
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@retval FALSE if this is core thread
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**/
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BOOLEAN
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IsSecondaryThread (
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VOID
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)
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{
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UINT32 ApicID;
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EFI_CPUID_REGISTER CpuidRegisters;
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UINT8 CpuCount;
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UINT8 CoreCount;
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UINT8 CpuPerCore;
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UINT32 Mask;
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ApicID = GetCpuApicId ();
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AsmCpuid (
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CPUID_VERSION_INFO,
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&CpuidRegisters.RegEax,
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&CpuidRegisters.RegEbx,
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&CpuidRegisters.RegEcx,
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&CpuidRegisters.RegEdx
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);
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if ((CpuidRegisters.RegEdx & 0x10000000) == 0) {
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return FALSE;
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}
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CpuCount = (UINT8) ((CpuidRegisters.RegEbx >> 16) & 0xff);
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if (CpuCount == 1) {
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return FALSE;
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}
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AsmCpuid (
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CPUID_SIGNATURE,
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&CpuidRegisters.RegEax,
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&CpuidRegisters.RegEbx,
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&CpuidRegisters.RegEcx,
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&CpuidRegisters.RegEdx
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);
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if (CpuidRegisters.RegEax > 3) {
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CoreCount = GetMaxSupportedCoreCount ();
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} else {
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CoreCount = 1;
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}
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///
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/// Assumes there is symmetry across core boundary, i.e. each core within a package has the same number of logical processors
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///
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if (CpuCount == CoreCount) {
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return FALSE;
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}
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CpuPerCore = CpuCount / CoreCount;
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///
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/// Assume 1 Core has no more than 8 threads
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///
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if (CpuPerCore == 2) {
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Mask = 0x1;
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} else if (CpuPerCore <= 4) {
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Mask = 0x3;
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} else {
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Mask = 0x7;
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}
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if ((ApicID & Mask) == 0) {
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return FALSE;
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} else {
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return TRUE;
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}
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}
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