/** @file
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This file contains CPU Gnvs Struct specific to processor
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _POWER_MGMT_NVS_STRUCT_H_
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#define _POWER_MGMT_NVS_STRUCT_H_
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//
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// Processor Power Management GlobalNvs Revisions
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//
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#define CPU_GLOBAL_NVS_AREA_REVISION 2
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//
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// Structure Declarations
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//
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#pragma pack(1)
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///
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/// Config TDP level settings.
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///
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typedef struct {
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UINT16 CtdpPowerLimit1; ///< CTDP Power Limit1
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UINT16 CtdpPowerLimit2; ///< CTDP Power Limit2
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UINT8 CtdpPowerLimitWindow; ///< CTDP Power Limit Time Window
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UINT8 CtdpCtc; ///< CTDP CTC
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UINT8 CtdpTar; ///< CTDP TAR
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UINT8 CtdpPpc; ///< CTDP PPC
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} CTDP_LEVEL_SETTINGS;
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///
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/// CPU Global NVS Area definition
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///
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typedef struct {
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/**
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This member specifies the revision of the CPU_GLOBAL_NVS_AREA. This field is used to indicate backward
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compatible changes to the NVS AREA. Any such changes to this PPI will result in an update in the revision number.
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<b>Revision 1</b>:
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- Initial version.
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**/
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UINT8 Revision; ///< (0) CPU GlobalNvs Revision
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//
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// PPM Flag Values
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//
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UINT32 PpmFlags; ///< (1-4) PPM Flags
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UINT8 Reserved; ///< (5) Reserved
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//
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// Thermal Configuration Values
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//
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UINT8 AutoCriticalTripPoint; ///< (6) Auto Critical Trip Point
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UINT8 AutoPassiveTripPoint; ///< (7) Auto Passive Trip Point
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UINT8 AutoActiveTripPoint; ///< (8) Auto Active Trip Point
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UINT32 Cpuid; ///< (9) CPUID
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//
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// ConfigTDP Values
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//
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UINT8 ConfigurablePpc; ///< (13) Boot Mode vlues for _PPC
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//
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// ConfigTDP Level settngs
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//
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UINT8 CtdpLevelsSupported; ///< (14) ConfigTdp Number Of Levels
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UINT8 ConfigTdpBootModeIndex; ///< (15) CTDP Boot Mode Index
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///
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/// (16) CTDP Level 0 Power Limit1
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/// (18) CTDP Level 0 Power Limit2
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/// (20) CTDP Level 0 Power Limit1 Time Window
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/// (21) CTDP Level 0 CTC
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/// (22) CTDP Level 0 TAR
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/// (23) CTDP Level 0 PPC
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/// (24) CTDP Level 1 Power Limit1
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/// (26) CTDP Level 1 Power Limit2
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/// (28) CTDP Level 1 Power Limit1 Time Window
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/// (29) CTDP Level 1 CTC
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/// (30) CTDP Level 1 TAR
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/// (31) CTDP Level 1 PPC
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/// (32) CTDP Level 2 Power Limit1
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/// (34) CTDP Level 2 Power Limit2
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/// (36) CTDP Level 2 Power Limit1 Time Window
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/// (37) CTDP Level 2 CTC
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/// (38) CTDP Level 2 TAR
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/// (39) CTDP Level 2 PPC
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///
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CTDP_LEVEL_SETTINGS CtdpLevelSettings[3];
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//
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// Mwait Hints and Latency values for C3/C6/C7/C7S
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//
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UINT8 C3MwaitValue; ///< (40) Mwait Hint value for C3
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UINT8 C6MwaitValue; ///< (41) Mwait Hint value for C6
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UINT8 C7MwaitValue; ///< (42) Mwait Hint value for C6
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UINT8 CDMwaitValue; ///< (43) Mwait Hint value for C7/C8/C9/C10
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UINT16 C3Latency; ///< (44-45) Latency value for C3
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UINT16 C6Latency; ///< (46-47) Latency Value for C6
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UINT16 C7Latency; ///< (48-49) Latency Value for C6
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UINT16 CDLatency; ///< (50-51) Latency Value for C7/C8/C9/C10
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UINT16 CDIOLevel; ///< (52-53) IO Level Value for C7/C8/C9/C10
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UINT16 CDPowerValue; ///< (54-55) Power Value for C7/C8/C9/C10
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UINT8 MiscPowerManagementFlags; ///< (55) MiscPowerManagementFlags
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//
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// DTS
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//
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UINT8 EnableDigitalThermalSensor; ///< (57) DTS Function enable
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UINT8 BspDigitalThermalSensorTemperature; ///< (58) Temperature of BSP
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UINT8 ApDigitalThermalSensorTemperature; ///< (59) Temperature of AP
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UINT8 DigitalThermalSensorSmiFunction; ///< (60) SMI function call via DTS IO Trap
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UINT8 PackageDTSTemperature; ///< (61) Package temperature
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UINT8 IsPackageTempMSRAvailable; ///< (62) Package Temperature MSR available
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UINT8 Ap2DigitalThermalSensorTemperature; ///< (63) Temperature of the second AP
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UINT8 Ap3DigitalThermalSensorTemperature; ///< (64) Temperature of the third AP
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//
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// BIOS Guard
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//
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UINT64 BiosGuardMemAddress; ///< (65-72) BIOS Guard Memory Address for Tool Interface
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UINT8 BiosGuardMemSize; ///< (73) BIOS Guard Memory Size for Tool Interface
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UINT16 BiosGuardIoTrapAddress; ///< (74-75) IoTrap Address for Tool Interface
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UINT16 BiosGuardIoTrapLength; ///< (76-77) IoTrap Length for Tool Interface
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//
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// DTS I/O Trap
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//
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UINT16 DtsIoTrapAddress; ///< (78-79) DTS IO trap Address
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UINT8 DtsIoTrapLength; ///< (80) DTS IO trap Length
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UINT8 DtsAcpiEnable; ///< (81) DTS is in ACPI Mode Enabled
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//
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// Software Guard Extension
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//
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UINT8 SgxStatus; ///< (82) SE Status
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UINT64 EpcBaseAddress; ///< (83-90) EPC Base Address
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UINT64 EpcLength; ///< (91-98) EPC Length
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//
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// HWP
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//
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UINT8 HwpVersion; ///< (99) HWP Status
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UINT16 HwpIoTrapAddress; ///< (100-101) IoTrap Address for HWP
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UINT16 HwpIoTrapLength; ///< (102-103) IoTrap Length for HWP
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UINT8 PowerState; ///< (104) Power State
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UINT8 EnableHdcPolicy; ///< (105) Hardware Duty Cycling Policy
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UINT8 HwpInterruptStatus; ///< (106) HWP Interrupt Status
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UINT8 DtsInterruptStatus; ///< (107) DTS Interrupt Status
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} CPU_GLOBAL_NVS;
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#pragma pack()
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typedef struct _CPU_GLOBAL_NVS_AREA_CONFIG {
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CPU_GLOBAL_NVS *Area;
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} CPU_GLOBAL_NVS_AREA_CONFIG;
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typedef struct _FVID_HEADER {
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UINT32 Stepping; ///< Matches value returned by CPUID function 1
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UINT16 MaxBusRatio; ///< Matches BUS_RATIO_MAX field in PERF_STS_MSR
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UINT16 EistStates; ///< Number of states of FVID (N)
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} FVID_HEADER;
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typedef struct _FVID_STATE {
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UINT32 State; ///< State Number (0 - N-1)
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UINT16 BusRatio; ///< BUS_RATIO_SEL value to be written to PERF_CTL
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UINT32 Power; ///< Typical power consumed by CPU in this state
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UINT32 Limit16State; ///< State Number (0 - N-1) with limit 16 P-states
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UINT16 Limit16BusRatio; ///< BUS_RATIO_SEL value to be written to PERF_CTL with limit 16 P-states
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UINT32 Limit16Power; ///< Typical power consumed by CPU in this state with limit 16 P-states
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} FVID_STATE;
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typedef union _FVID_TABLE {
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FVID_HEADER FvidHeader;
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FVID_STATE FvidState;
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UINT64 FvidData;
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} FVID_TABLE;
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#endif
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