/** @file
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Protocol used to report CPU information
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _CPU_INFO_H_
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#define _CPU_INFO_H_
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#include <CpuDataStruct.h>
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typedef struct _CPU_INFO_PROTOCOL CPU_INFO_PROTOCOL;
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extern EFI_GUID gCpuInfoProtocolGuid;
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//
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// DXE_CPU_INFO_PROTOCOL revisions
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//
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#define CPU_INFO_PROTOCOL_REVISION 1
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//
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// Processor feature definitions.
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//
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#define TXT_SUPPORT BIT0
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#define VMX_SUPPORT BIT1
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#define XD_SUPPORT BIT2
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#define DCA_SUPPORT BIT3
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#define X2APIC_SUPPORT BIT4
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#define AES_SUPPORT BIT5
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#define HT_SUPPORT BIT6
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#define DEBUG_SUPPORT BIT7
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#define DEBUG_LOCK_SUPPORT BIT8
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#define PROC_TRACE_SUPPORT BIT9
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#define HDC_SUPPORT BIT10
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#pragma pack(1)
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///
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/// Cache descriptor information
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///
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typedef struct {
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UINT8 Desc; ///< Cache Descriptor
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UINT8 Level; ///< Cache Level
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UINT8 Type; ///< Cache Type. 0: Data, 1: Instruction, 3: Unified
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UINT32 Size; ///< Cache Size.
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UINT16 Associativity; ///< Cache Ways of Associativity.
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} CACHE_DESCRIPTOR_INFO;
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///
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/// Processor information
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///
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typedef struct {
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UINT32 CpuSignature; ///< Processor signature and version information.
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UINT64 Features; ///< Features availability in the CPU based on reading ECX after doing Asmcpuid(EAX=1).
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CHAR8 *BrandString; ///< Processor Brand String.
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UINT8 NumSupportedCores; ///< Total Number of Supported Cores in CPU Package. If Dual core, 2 cores.
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UINT8 NumSupportedThreadsPerCore; ///< Number of Supported Threads per Core.
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UINT8 NumCores; ///< Number of Enabled or Active Cores.
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UINT8 NumHts; ///< Number of Enabled Threads per Core. This will be 1 or 2.
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UINT32 IntendedFreq; ///< Maximum non turbo ratio in MHz
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UINT32 ActualFreq; ///< Actual frequency in MHz
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UINT32 Voltage; ///< Current operating voltage.
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CACHE_DESCRIPTOR_INFO *CacheInfo; ///< Cache descriptor information.
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UINT8 MaxCacheSupported; ///< Maximum cache supported.
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UINT8 SmmbaseSwSmiNumber; ///< Software SMI Number from Smbase.
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UINT16 NumberOfPStates; ///< Number of P-States.
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} CPU_INFO;
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///
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/// This HOB is data structure representing two different address location in SMRAM to hold SMRAM CPU DATA.
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///
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typedef struct {
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EFI_PHYSICAL_ADDRESS LockBoxData; ///< First location (address) of SMRAM CPU DATA.
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EFI_PHYSICAL_ADDRESS SmramCpuData; ///< Second location (Address) of SMRAM CPU DATA.
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UINT64 LockBoxSize; ///< Size of SMRAM CPU DATA.
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} SMRAM_CPU_INFO;
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///
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/// SGX Information
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///
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typedef struct {
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UINT64 SgxSinitNvsData; ///< Sinit SE SVN Version saved and passed back in next boot
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} SGX_INFO;
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#pragma pack()
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///
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/// This protocol provides information about the common features available in this CPU.
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///
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struct _CPU_INFO_PROTOCOL {
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/**
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Revision for the protocol structure.
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Any backwards compatible changes to this protocol will result in an update in the revision number.
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Major changes will require publication of a new protocol
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<b>Revision 1</b>:
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- Initial version
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**/
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UINT8 Revision;
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/**
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CPU Supported Feature.
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- BIT0: If set then processor supports TXT.
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- BIT1: If set then processor supports virtual mode extensions.
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- BIT2: If set then processor supports execute disable bit.
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- BIT3: If set then processor supports DCA.
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- BIT4: If set then processor supports X2APIC.
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- BIT5: If set then processor supports Advanced Encryption Standard.
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- BIT6: If set then processor supports hyperthreading.
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- BIT7: If set then processor supports debug interface.
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- BIT8: If set then processor supports debug interface lock.
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- BIT9: If set then processor supports processor trace.
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- BIT10: If Set then processor supports supports HDC.
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**/
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UINT64 CpuCommonFeatures;
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CPU_INFO *CpuInfo; ///< Processor Basic Information
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SMRAM_CPU_INFO *SmramCpuInfo; ///< SMRAM CPU Information
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SGX_INFO *SgxInfo; ///< SGX Information
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};
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#endif
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