/** @file
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This file contains define definitions specific to processor
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _POWER_MGMT_DEFINITIONS_H_
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#define _POWER_MGMT_DEFINITIONS_H_
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#define CSTATE_SUPPORTED 0x1
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#define ENHANCED_CSTATE_SUPPORTED 0x2
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#define C6_C7_SHORT_LATENCY_SUPPORTED 0x01
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#define C6_C7_LONG_LATENCY_SUPPORTED 0x02
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#define C7s_SHORT_LATENCY_SUPPORTED 0x03
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#define C7s_LONG_LATENCY_SUPPORTED 0x04
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//
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// Voltage offset definitions
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//
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#define OC_LIB_OFFSET_ADAPTIVE 0
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#define OC_LIB_OFFSET_OVERRIDE 1
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//
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// Platform Power Management Flags Bit Definitions:
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// These defines are also used in CPU0CST.ASL to check platform configuration
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// and build C-state table accordingly.
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//
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#define PPM_EIST BIT0 ///< Enhanced Intel Speed Step Technology.
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#define PPM_C1 BIT1 ///< C1 enabled, supported.
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#define PPM_C1E BIT2 ///< C1E enabled.
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#define PPM_C3 BIT3 ///< C3 enabled, supported.
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#define PPM_C6 BIT4 ///< C6 enabled, supported.
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#define PPM_C7 BIT5 ///< C7 enabled, supported.
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#define PPM_C7S BIT6 ///< C7S enabled, supported
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#define PPM_TM BIT7 ///< Adaptive Thermal Monitor.
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#define PPM_TURBO BIT8 ///< Long duration turbo mode
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#define PPM_CMP BIT9 ///< CMP.
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#define PPM_TSTATES BIT10 ///< CPU throttling states
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#define PPM_MWAIT_EXT BIT11 ///< MONITIOR/MWAIT Extensions supported.
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#define PPM_EEPST BIT12 ///< Energy efficient P-State Feature enabled
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#define PPM_TSTATE_FINE_GRAINED BIT13 ///< Fine grained CPU Throttling states
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#define PPM_CD BIT14 ///< Deep Cstate - C8/C9/C10
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#define PPM_TIMED_MWAIT BIT15 ///< Timed Mwait support
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#define C6_LONG_LATENCY_ENABLE BIT16 ///< 1=C6 Long and Short,0=C6 Short only
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#define C7_LONG_LATENCY_ENABLE BIT17 ///< 1=C7 Long and Short,0=C7 Short only
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#define C7s_LONG_LATENCY_ENABLE BIT18 ///< 1=C7s Long and Short,0=C7s Short only
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#define PPM_C8 BIT19 ///< 1= C8 enabled/supported
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#define PPM_C9 BIT20 ///< 1= C9 enabled/supported
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#define PPM_C10 BIT21 ///< 1= C10 enabled/supported
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#define PPM_HWP BIT22 ///< 1= HWP enabled/supported
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#define PPM_HWP_LVT BIT23 ///< 1= HWP LVT enabled/supported
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#define PPM_OC_UNLOCKED BIT24 ///< 1= Overclocking fully unlocked
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#define PPM_C_STATES 0x7A ///< PPM_C1 + PPM_C3 + PPM_C6 + PPM_C7 + PPM_C7S
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#define C3_LATENCY 0x4E
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#define C6_C7_SHORT_LATENCY 0x76
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#define C6_C7_LONG_LATENCY 0x94
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#define C8_LATENCY 0xFA
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#define C9_LATENCY 0x14C
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#define C10_LATENCY 0x3F2
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//
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// The following definitions are based on assumed location for the ACPI
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// Base Address. Modify as necessary base on platform-specific requirements.
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//
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#define PCH_ACPI_PBLK 0x1810
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#define PCH_ACPI_LV2 0x1814
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#define PCH_ACPI_LV3 0x1815
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#define PCH_ACPI_LV4 0x1816
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#define PCH_ACPI_LV6 0x1818
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#define PCH_ACPI_LV5 0x1817
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#define PCH_ACPI_LV7 0x1819
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//
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// C-State Latency (us) and Power (mW) for C1
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//
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#define C1_LATENCY 1
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#define C1_POWER 0x3E8
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#define C3_POWER 0x1F4
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#define C6_POWER 0x15E
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#define C7_POWER 0xC8
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#define C8_POWER 0xC8
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#define C9_POWER 0xC8
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#define C10_POWER 0xC8
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#define PID_DOMAIN_KP 0
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#define PID_DOMAIN_KI 1
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#define PID_DOMAIN_KD 2
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#define MAILBOX_PARAM_1_OFFSET 8
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///
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/// VR Domain Definitions
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///
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#define SKL_VR_DOMAIN_SA 0x0
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#define SKL_VR_DOMAIN_IA 0x1
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#define SKL_VR_DOMAIN_GTUS 0x2
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#define SKL_VR_DOMAIN_GTS 0x3
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#endif
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