/** @file
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This file declares various data structures used in CPU reference code.
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Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _CPU_DATA_STRUCT_H
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#define _CPU_DATA_STRUCT_H
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//
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// The reason for changing the state of the processor Only applies to Disabling processors.
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// In future, we can add add/remove support
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//
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#define CPU_CAUSE_NOT_DISABLED 0x0000
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#define CPU_CAUSE_INTERNAL_ERROR 0x0001
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#define CPU_CAUSE_THERMAL_ERROR 0x0002
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#define CPU_CAUSE_SELFTEST_FAILURE 0x0004
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#define CPU_CAUSE_PREBOOT_TIMEOUT 0x0008
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#define CPU_CAUSE_FAILED_TO_START 0x0010
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#define CPU_CAUSE_CONFIG_ERROR 0x0020
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#define CPU_CAUSE_USER_SELECTION 0x0080
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#define CPU_CAUSE_BY_ASSOCIATION 0x0100
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#define CPU_CAUSE_UNSPECIFIED 0x8000
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#define MAX_MICROCODE_PATCH_SIZE 0x20000
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typedef UINT32 CPU_STATE_CHANGE_CAUSE;
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///
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/// The data structure is used retrieve data required for MP initialization during S3 resume.
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///
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typedef struct {
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BOOLEAN APState; ///< Indicates whether the newstate of the AP is enabled or disabled.
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BOOLEAN S3BootPath; ///< TRUE: S3 Boot path. FALSE: Regular boot path.
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EFI_PHYSICAL_ADDRESS WakeUpBuffer; ///< Buffer location used during AP Initialization
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EFI_PHYSICAL_ADDRESS GdtrProfile; ///< Address of Global Descriptor Table
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EFI_PHYSICAL_ADDRESS IdtrProfile; ///< address of Interrupt Descriptor Table
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EFI_PHYSICAL_ADDRESS CpuPrivateData; ///< Address of CPU_PRIVATE_DATA structure
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EFI_PHYSICAL_ADDRESS StackAddress; ///< Address of APs's stacks
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EFI_PHYSICAL_ADDRESS SmramBase; ///< @deprecated Address of SMRAM base as seen by software executing on the processors
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EFI_PHYSICAL_ADDRESS SmmStartImageBase; ///< @deprecated Address of SMM Start Image Base
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UINT32 SmmStartImageSize; ///< @deprecated Size of SMM Start Image
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UINT32 NumberOfCpus; ///< Number of processors
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} ACPI_CPU_DATA;
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///
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/// CPU information stored in SMRAM during DXE.
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///
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typedef struct {
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//
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// Guid as Signature.
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//
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EFI_GUID HeaderGuid;
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EFI_PHYSICAL_ADDRESS AcpiCpuPointer;
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ACPI_CPU_DATA AcpiCpuData;
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//
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// It points the data defined below.
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//
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EFI_PHYSICAL_ADDRESS GdtrProfileOffset;
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EFI_PHYSICAL_ADDRESS GdtOffset;
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EFI_PHYSICAL_ADDRESS IdtrProfileOffset;
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EFI_PHYSICAL_ADDRESS IdtOffset;
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EFI_PHYSICAL_ADDRESS CpuPrivateDataOffset;
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EFI_PHYSICAL_ADDRESS S3BspMtrrTableOffset;
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///
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/// We need put all the data buffer here as well.
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/// These data will be copied to original location in S3.
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///
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//
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// DataBuffer size
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//
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UINT32 GdtrProfileSize;
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UINT32 GdtSize;
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UINT32 IdtrProfileSize;
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UINT32 IdtSize;
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UINT32 CpuPrivateDataSize;
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UINT32 S3BspMtrrTableSize;
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} SMRAM_CPU_DATA;
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///
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/// Structure to hold the return value of AsmCpuid instruction
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///
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typedef struct {
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UINT32 RegEax; ///< Value of EAX.
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UINT32 RegEbx; ///< Value of EBX.
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UINT32 RegEcx; ///< Value of ECX.
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UINT32 RegEdx; ///< Value of EDX.
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} EFI_CPUID_REGISTER;
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///
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/// Structure to describe microcode header
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///
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typedef struct {
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UINT32 HeaderVersion; ///< Version number of the update header.
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UINT32 UpdateRevision; ///< Unique version number for the update.
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UINT32 Date; ///< Date of the update creation.
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UINT32 ProcessorId; ///< Signature of the processor that requires this update.
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UINT32 Checksum; ///< Checksum of update data and header.
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UINT32 LoaderRevision; ///< Version number of the microcode loader program.
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UINT32 ProcessorFlags; ///< Lower 4 bits denoting platform type information.
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UINT32 DataSize; ///< Size of encoded data in bytes.
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UINT32 TotalSize; ///< Total size of microcode update in bytes.
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UINT8 Reserved[12]; ///< Reserved bits.
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} CPU_MICROCODE_HEADER;
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///
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/// Structure to describe the extended signature table header of the microcode update
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///
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typedef struct {
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UINT32 ExtendedSignatureCount; ///< Number of extended signature structures.
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UINT32 ExtendedTableChecksum; ///< Checksum of update extended processor signature table.
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UINT8 Reserved[12]; ///< Reserved bits.
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} CPU_MICROCODE_EXTENDED_TABLE_HEADER;
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///
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/// Structure to describe the data of the extended table of the microcode update
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///
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typedef struct {
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UINT32 ProcessorSignature; ///< Extended signature of the processor that requires this update
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UINT32 ProcessorFlag; ///< Lower 4 bits denoting platform type information
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UINT32 ProcessorChecksum; ///< checksum of each of the extended update
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} CPU_MICROCODE_EXTENDED_TABLE;
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#pragma pack(1)
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///
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/// MSR_REGISTER definition as a Union of QWORDS, DWORDS and BYTES
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///
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typedef union _MSR_REGISTER {
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UINT64 Qword; ///< MSR value in 64 bit QWORD.
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///
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/// MSR value represented in two DWORDS
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///
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struct {
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UINT32 Low; ///< Lower DWORD of the 64 bit MSR value.
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UINT32 High; ///< Higher DWORD of the 64 bit MSR value.
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} Dwords;
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///
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/// MSR value represented in eight bytes.
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///
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struct {
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UINT8 FirstByte; ///< First byte of the 64 bit MSR value.
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UINT8 SecondByte; ///< Second byte of the 64 bit MSR value.
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UINT8 ThirdByte; ///< Third byte of the 64 bit MSR value.
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UINT8 FouthByte; ///< Fourth byte of the 64 bit MSR value.
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UINT8 FifthByte; ///< Fifth byte of the 64 bit MSR value.
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UINT8 SixthByte; ///< Sixth byte of the 64 bit MSR value.
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UINT8 SeventhByte; ///< Seventh byte of the 64 bit MSR value.
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UINT8 EighthByte; ///< Eigth byte of the 64 bit MSR value.
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} Bytes;
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} MSR_REGISTER;
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///
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/// Store BIST data for BSP.
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///
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typedef struct {
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UINT32 ApicId; ///< APIC ID
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UINT32 Health; ///< BIST result
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} BIST_HOB_DATA;
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///
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/// Processor trace buffer size selection.
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///
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typedef enum {
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Enum4K = 0,
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Enum8K,
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Enum16K,
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Enum32K,
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Enum64K,
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Enum128K,
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Enum256K,
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Enum512K,
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Enum1M,
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Enum2M,
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Enum4M,
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Enum8M,
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Enum16M,
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Enum32M,
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Enum64M,
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Enum128M,
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EnumProcTraceMemDisable
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} PROC_TRACE_MEM_SIZE;
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#pragma pack()
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#endif
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