/** @file
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FSP CPU Data Config Block.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _CPU_CONFIG_FSP_DATA_H_
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#define _CPU_CONFIG_FSP_DATA_H_
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#pragma pack (push,1)
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typedef union {
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struct {
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/**
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Enable or Disable Advanced Encryption Standard (AES) feature.
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For some countries, this should be disabled for legal reasons.
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- 0: Disable
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- <b>1: Enable</b>
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**/
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UINT32 AesEnable : 1;
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/**
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Processor Early Power On Configuration FCLK setting.
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- <b>0: 800 MHz (ULT/ULX)</b>.
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- <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.
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- 2: 400 MHz.
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- 3: Reserved.
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**/
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UINT32 FClkFrequency : 2;
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UINT32 EnableRsr : 1; ///< Enable or Disable RSR feature; 0: Disable; <b>1: Enable </b>
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/**
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Policies to obtain CPU temperature.
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- <b>0: ACPI thermal management uses EC reported temperature values</b>.
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- 1: ACPI thermal management uses DTS SMM mechanism to obtain CPU temperature values.
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- 2: ACPI Thermal Management uses EC reported temperature values and DTS SMM is used to handle Out of Spec condition.
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**/
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UINT32 EnableDts : 2;
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UINT32 SmmbaseSwSmiNumber : 8; ///< Software SMI number for handler to save CPU information in SMRAM.
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/**
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Enable or Disable Virtual Machine Extensions (VMX) feature.
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- 0: Disable
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- <b>1: Enable</b>
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**/
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UINT32 VmxEnable : 1;
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/**
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Enable or Disable Trusted Execution Technology (TXT) feature.
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- 0: Disable
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- <b>1: Enable</b>
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**/
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UINT32 TxtEnable : 1;
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UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0.
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UINT32 RsvdBits : 15; ///< Reserved for future use
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UINT32 Reserved;
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} Bits;
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UINT32 Uint32[2];
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} CPU_CONFIG_FSP_DATA;
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#pragma pack (pop)
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#endif // _CPU_CONFIG_FSP_DATA_H_
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