/** @file
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Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "DmaProtection.h"
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UINTN mVtdUnitNumber;
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VTD_UNIT_INFORMATION *mVtdUnitInformation;
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BOOLEAN mVtdEnabled;
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/**
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Flush VTD page table and context table memory.
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This action is to make sure the IOMMU engine can get final data in memory.
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@param[in] VtdIndex The index used to identify a VTd engine.
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@param[in] Base The base address of memory to be flushed.
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@param[in] Size The size of memory in bytes to be flushed.
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**/
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VOID
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FlushPageTableMemory (
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IN UINTN VtdIndex,
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IN UINTN Base,
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IN UINTN Size
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)
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{
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if (mVtdUnitInformation[VtdIndex].ECapReg.Bits.C == 0) {
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WriteBackDataCacheRange ((VOID *)Base, Size);
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}
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}
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/**
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Flush VTd engine write buffer.
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@param[in] VtdIndex The index used to identify a VTd engine.
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**/
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VOID
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FlushWriteBuffer (
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IN UINTN VtdIndex
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)
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{
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UINT32 Reg32;
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if (mVtdUnitInformation[VtdIndex].CapReg.Bits.RWBF != 0) {
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Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GSTS_REG);
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MmioWrite32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GCMD_REG, Reg32 | B_GMCD_REG_WBF);
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do {
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Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GSTS_REG);
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} while ((Reg32 & B_GSTS_REG_WBF) != 0);
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}
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}
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/**
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Perpare cache invalidation interface.
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@param[in] VtdIndex The index used to identify a VTd engine.
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@retval EFI_SUCCESS The operation was successful.
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@retval EFI_UNSUPPORTED Invalidation method is not supported.
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@retval EFI_OUT_OF_RESOURCES A memory allocation failed.
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**/
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EFI_STATUS
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PerpareCacheInvalidationInterface (
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IN UINTN VtdIndex
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)
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{
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UINT16 QueueSize;
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UINT64 Reg64;
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UINT32 Reg32;
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if (mVtdUnitInformation[VtdIndex].VerReg.Bits.Major <= 6) {
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mVtdUnitInformation[VtdIndex].EnableQueuedInvalidation = 0;
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DEBUG ((DEBUG_INFO, "Use Register-based Invalidation Interface for engine [%d]\n", VtdIndex));
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return EFI_SUCCESS;
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}
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if (mVtdUnitInformation[VtdIndex].ECapReg.Bits.QI == 0) {
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DEBUG ((DEBUG_ERROR, "Hardware does not support queued invalidations interface for engine [%d]\n", VtdIndex));
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return EFI_UNSUPPORTED;
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}
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mVtdUnitInformation[VtdIndex].EnableQueuedInvalidation = 1;
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DEBUG ((DEBUG_INFO, "Use Queued Invalidation Interface for engine [%d]\n", VtdIndex));
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Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GSTS_REG);
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if ((Reg32 & B_GSTS_REG_QIES) != 0) {
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DEBUG ((DEBUG_ERROR,"Queued Invalidation Interface was enabled.\n"));
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Reg32 &= (~B_GSTS_REG_QIES);
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MmioWrite32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GCMD_REG, Reg32);
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do {
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Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GSTS_REG);
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} while ((Reg32 & B_GSTS_REG_QIES) != 0);
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}
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//
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// Initialize the Invalidation Queue Tail Register to zero.
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//
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MmioWrite64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_IQT_REG, 0);
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//
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// Setup the IQ address, size and descriptor width through the Invalidation Queue Address Register
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//
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QueueSize = 0;
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mVtdUnitInformation[VtdIndex].QiDescLength = 1 << (QueueSize + 8);
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mVtdUnitInformation[VtdIndex].QiDesc = (QI_DESC *) AllocatePages (EFI_SIZE_TO_PAGES(sizeof(QI_DESC) * mVtdUnitInformation[VtdIndex].QiDescLength));
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if (mVtdUnitInformation[VtdIndex].QiDesc == NULL) {
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mVtdUnitInformation[VtdIndex].QiDescLength = 0;
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DEBUG ((DEBUG_ERROR,"Could not Alloc Invalidation Queue Buffer.\n"));
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return EFI_OUT_OF_RESOURCES;
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}
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DEBUG ((DEBUG_INFO, "Invalidation Queue Length : %d\n", mVtdUnitInformation[VtdIndex].QiDescLength));
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Reg64 = (UINT64)(UINTN)mVtdUnitInformation[VtdIndex].QiDesc;
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Reg64 |= QueueSize;
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MmioWrite64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_IQA_REG, Reg64);
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//
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// Enable the queued invalidation interface through the Global Command Register.
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// When enabled, hardware sets the QIES field in the Global Status Register.
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//
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Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GSTS_REG);
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Reg32 |= B_GMCD_REG_QIE;
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MmioWrite32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GCMD_REG, Reg32);
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DEBUG ((DEBUG_INFO, "Enable Queued Invalidation Interface. GCMD_REG = 0x%x\n", Reg32));
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do {
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Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GSTS_REG);
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} while ((Reg32 & B_GSTS_REG_QIES) == 0);
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mVtdUnitInformation[VtdIndex].QiFreeHead = 0;
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return EFI_SUCCESS;
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}
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/**
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Disable queued invalidation interface.
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@param[in] VtdIndex The index used to identify a VTd engine.
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**/
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VOID
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DisableQueuedInvalidationInterface (
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IN UINTN VtdIndex
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)
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{
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UINT32 Reg32;
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if (mVtdUnitInformation[VtdIndex].EnableQueuedInvalidation != 0) {
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Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GSTS_REG);
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Reg32 &= (~B_GMCD_REG_QIE);
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MmioWrite32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GCMD_REG, Reg32);
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DEBUG ((DEBUG_INFO, "Disable Queued Invalidation Interface. GCMD_REG = 0x%x\n", Reg32));
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do {
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Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GSTS_REG);
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} while ((Reg32 & B_GSTS_REG_QIES) != 0);
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if (mVtdUnitInformation[VtdIndex].QiDesc != NULL) {
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FreePages(mVtdUnitInformation[VtdIndex].QiDesc, EFI_SIZE_TO_PAGES(sizeof(QI_DESC) * mVtdUnitInformation[VtdIndex].QiDescLength));
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mVtdUnitInformation[VtdIndex].QiDesc = NULL;
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mVtdUnitInformation[VtdIndex].QiDescLength = 0;
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}
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mVtdUnitInformation[VtdIndex].EnableQueuedInvalidation = 0;
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}
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}
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/**
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Check Queued Invalidation Fault.
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@param[in] VtdIndex The index used to identify a VTd engine.
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@retval EFI_SUCCESS The operation was successful.
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@retval RETURN_DEVICE_ERROR A fault is detected.
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**/
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EFI_STATUS
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QueuedInvalidationCheckFault (
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IN UINTN VtdIndex
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)
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{
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UINT32 FaultReg;
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FaultReg = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FSTS_REG);
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if (FaultReg & B_FSTS_REG_IQE) {
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DEBUG((DEBUG_ERROR, "Detect Invalidation Queue Error [0x%08x]\n", FaultReg));
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FaultReg |= B_FSTS_REG_IQE;
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MmioWrite32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FSTS_REG, FaultReg);
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return RETURN_DEVICE_ERROR;
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}
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if (FaultReg & B_FSTS_REG_ITE) {
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DEBUG((DEBUG_ERROR, "Detect Invalidation Time-out Error [0x%08x]\n", FaultReg));
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FaultReg |= B_FSTS_REG_ITE;
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MmioWrite32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FSTS_REG, FaultReg);
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return RETURN_DEVICE_ERROR;
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}
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if (FaultReg & B_FSTS_REG_ICE) {
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DEBUG((DEBUG_ERROR, "Detect Invalidation Completion Error [0x%08x]\n", FaultReg));
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FaultReg |= B_FSTS_REG_ICE;
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MmioWrite32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FSTS_REG, FaultReg);
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return RETURN_DEVICE_ERROR;
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}
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return EFI_SUCCESS;
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}
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/**
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Submit the queued invalidation descriptor to the remapping
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hardware unit and wait for its completion.
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@param[in] VtdIndex The index used to identify a VTd engine.
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@param[in] Desc The invalidate descriptor
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@retval EFI_SUCCESS The operation was successful.
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@retval RETURN_DEVICE_ERROR A fault is detected.
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@retval EFI_INVALID_PARAMETER Parameter is invalid.
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**/
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EFI_STATUS
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SubmitQueuedInvalidationDescriptor (
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IN UINTN VtdIndex,
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IN QI_DESC *Desc
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)
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{
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EFI_STATUS Status;
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UINT16 QiDescLength;
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QI_DESC *BaseDesc;
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UINT64 Reg64Iqt;
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UINT64 Reg64Iqh;
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if (Desc == NULL) {
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return EFI_INVALID_PARAMETER;
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}
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QiDescLength = mVtdUnitInformation[VtdIndex].QiDescLength;
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BaseDesc = mVtdUnitInformation[VtdIndex].QiDesc;
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DEBUG((DEBUG_INFO, "[%d] Submit QI Descriptor [0x%08x, 0x%08x] Free Head (%d)\n", VtdIndex, Desc->Low, Desc->High, mVtdUnitInformation[VtdIndex].QiFreeHead));
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BaseDesc[mVtdUnitInformation[VtdIndex].QiFreeHead].Low = Desc->Low;
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BaseDesc[mVtdUnitInformation[VtdIndex].QiFreeHead].High = Desc->High;
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FlushPageTableMemory(VtdIndex, (UINTN) &BaseDesc[mVtdUnitInformation[VtdIndex].QiFreeHead], sizeof(QI_DESC));
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mVtdUnitInformation[VtdIndex].QiFreeHead = (mVtdUnitInformation[VtdIndex].QiFreeHead + 1) % QiDescLength;
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//
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// Update the HW tail register indicating the presence of new descriptors.
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//
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Reg64Iqt = mVtdUnitInformation[VtdIndex].QiFreeHead << DMAR_IQ_SHIFT;
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MmioWrite64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_IQT_REG, Reg64Iqt);
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Status = EFI_SUCCESS;
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do {
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Status = QueuedInvalidationCheckFault(VtdIndex);
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if (Status != EFI_SUCCESS) {
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DEBUG((DEBUG_ERROR,"Detect Queued Invalidation Fault.\n"));
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break;
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}
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Reg64Iqh = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_IQH_REG);
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} while (Reg64Iqt != Reg64Iqh);
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return Status;
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}
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/**
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Invalidate VTd context cache.
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@param[in] VtdIndex The index used to identify a VTd engine.
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**/
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EFI_STATUS
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InvalidateContextCache (
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IN UINTN VtdIndex
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)
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{
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UINT64 Reg64;
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QI_DESC QiDesc;
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if (mVtdUnitInformation[VtdIndex].EnableQueuedInvalidation == 0) {
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//
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// Register-based Invalidation
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//
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Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CCMD_REG);
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if ((Reg64 & B_CCMD_REG_ICC) != 0) {
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DEBUG ((DEBUG_ERROR,"ERROR: InvalidateContextCache: B_CCMD_REG_ICC is set for VTD(%d)\n",VtdIndex));
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return EFI_DEVICE_ERROR;
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}
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Reg64 &= ((~B_CCMD_REG_ICC) & (~B_CCMD_REG_CIRG_MASK));
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Reg64 |= (B_CCMD_REG_ICC | V_CCMD_REG_CIRG_GLOBAL);
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MmioWrite64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CCMD_REG, Reg64);
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do {
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Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CCMD_REG);
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} while ((Reg64 & B_CCMD_REG_ICC) != 0);
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} else {
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//
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// Queued Invalidation
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//
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QiDesc.Low = QI_CC_FM(0) | QI_CC_SID(0) | QI_CC_DID(0) | QI_CC_GRAN(1) | QI_CC_TYPE;
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QiDesc.High = 0;
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return SubmitQueuedInvalidationDescriptor(VtdIndex, &QiDesc);
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}
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return EFI_SUCCESS;
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}
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/**
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Invalidate VTd IOTLB.
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@param[in] VtdIndex The index used to identify a VTd engine.
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**/
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EFI_STATUS
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InvalidateIOTLB (
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IN UINTN VtdIndex
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)
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{
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UINT64 Reg64;
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QI_DESC QiDesc;
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if (mVtdUnitInformation[VtdIndex].EnableQueuedInvalidation == 0) {
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//
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// Register-based Invalidation
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//
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Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG);
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if ((Reg64 & B_IOTLB_REG_IVT) != 0) {
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DEBUG ((DEBUG_ERROR,"ERROR: InvalidateIOTLB: B_IOTLB_REG_IVT is set for VTD(%d)\n", VtdIndex));
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return EFI_DEVICE_ERROR;
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}
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Reg64 &= ((~B_IOTLB_REG_IVT) & (~B_IOTLB_REG_IIRG_MASK));
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Reg64 |= (B_IOTLB_REG_IVT | V_IOTLB_REG_IIRG_GLOBAL);
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MmioWrite64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG, Reg64);
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do {
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Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG);
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} while ((Reg64 & B_IOTLB_REG_IVT) != 0);
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} else {
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//
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// Queued Invalidation
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//
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QiDesc.Low = QI_IOTLB_DID(0) | QI_IOTLB_DR(CAP_READ_DRAIN(mVtdUnitInformation[VtdIndex].CapReg.Uint64)) | QI_IOTLB_DW(CAP_WRITE_DRAIN(mVtdUnitInformation[VtdIndex].CapReg.Uint64)) | QI_IOTLB_GRAN(1) | QI_IOTLB_TYPE;
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QiDesc.High = QI_IOTLB_ADDR(0) | QI_IOTLB_IH(0) | QI_IOTLB_AM(0);
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return SubmitQueuedInvalidationDescriptor(VtdIndex, &QiDesc);
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}
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return EFI_SUCCESS;
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}
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/**
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Invalid VTd global IOTLB.
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@param[in] VtdIndex The index of VTd engine.
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@retval EFI_SUCCESS VTd global IOTLB is invalidated.
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@retval EFI_DEVICE_ERROR VTd global IOTLB is not invalidated.
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**/
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EFI_STATUS
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InvalidateVtdIOTLBGlobal (
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IN UINTN VtdIndex
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)
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{
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if (!mVtdEnabled) {
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return EFI_SUCCESS;
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}
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DEBUG((DEBUG_VERBOSE, "InvalidateVtdIOTLBGlobal(%d)\n", VtdIndex));
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//
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// Write Buffer Flush before invalidation
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//
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FlushWriteBuffer (VtdIndex);
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//
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// Invalidate the context cache
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//
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if (mVtdUnitInformation[VtdIndex].HasDirtyContext) {
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InvalidateContextCache (VtdIndex);
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}
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//
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// Invalidate the IOTLB cache
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//
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if (mVtdUnitInformation[VtdIndex].HasDirtyContext || mVtdUnitInformation[VtdIndex].HasDirtyPages) {
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InvalidateIOTLB (VtdIndex);
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}
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return EFI_SUCCESS;
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}
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/**
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Prepare VTD configuration.
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**/
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VOID
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PrepareVtdConfig (
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VOID
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)
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{
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UINTN Index;
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UINTN DomainNumber;
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EFI_STATUS Status;
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for (Index = 0; Index < mVtdUnitNumber; Index++) {
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DEBUG ((DEBUG_INFO, "Dump VTd Capability (%d)\n", Index));
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mVtdUnitInformation[Index].VerReg.Uint32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_VER_REG);
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DumpVtdVerRegs (&mVtdUnitInformation[Index].VerReg);
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mVtdUnitInformation[Index].CapReg.Uint64 = MmioRead64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_CAP_REG);
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DumpVtdCapRegs (&mVtdUnitInformation[Index].CapReg);
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mVtdUnitInformation[Index].ECapReg.Uint64 = MmioRead64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_ECAP_REG);
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DumpVtdECapRegs (&mVtdUnitInformation[Index].ECapReg);
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if ((mVtdUnitInformation[Index].CapReg.Bits.SLLPS & BIT0) == 0) {
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DEBUG((DEBUG_WARN, "!!!! 2MB super page is not supported on VTD %d !!!!\n", Index));
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}
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if ((mVtdUnitInformation[Index].CapReg.Bits.SAGAW & BIT3) != 0) {
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DEBUG((DEBUG_INFO, "Support 5-level page-table on VTD %d\n", Index));
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}
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if ((mVtdUnitInformation[Index].CapReg.Bits.SAGAW & BIT2) != 0) {
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DEBUG((DEBUG_INFO, "Support 4-level page-table on VTD %d\n", Index));
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}
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if ((mVtdUnitInformation[Index].CapReg.Bits.SAGAW & (BIT3 | BIT2)) == 0) {
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DEBUG((DEBUG_ERROR, "!!!! Page-table type 0x%X is not supported on VTD %d !!!!\n", Index, mVtdUnitInformation[Index].CapReg.Bits.SAGAW));
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return ;
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}
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DomainNumber = (UINTN)1 << (UINT8)((UINTN)mVtdUnitInformation[Index].CapReg.Bits.ND * 2 + 4);
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if (mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceDataNumber >= DomainNumber) {
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DEBUG((DEBUG_ERROR, "!!!! Pci device Number(0x%x) >= DomainNumber(0x%x) !!!!\n", mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceDataNumber, DomainNumber));
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return ;
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}
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Status = PerpareCacheInvalidationInterface(Index);
|
if (EFI_ERROR (Status)) {
|
ASSERT(FALSE);
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return;
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}
|
}
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return ;
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}
|
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/**
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Disable PMR in all VTd engine.
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**/
|
VOID
|
DisablePmr (
|
VOID
|
)
|
{
|
UINT32 Reg32;
|
VTD_CAP_REG CapReg;
|
UINTN Index;
|
|
DEBUG ((DEBUG_INFO,"DisablePmr\n"));
|
for (Index = 0; Index < mVtdUnitNumber; Index++) {
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CapReg.Uint64 = MmioRead64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_CAP_REG);
|
if (CapReg.Bits.PLMR == 0 || CapReg.Bits.PHMR == 0) {
|
continue ;
|
}
|
|
Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_PMEN_ENABLE_REG);
|
if ((Reg32 & BIT0) != 0) {
|
MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_PMEN_ENABLE_REG, 0x0);
|
do {
|
Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_PMEN_ENABLE_REG);
|
} while((Reg32 & BIT0) != 0);
|
DEBUG ((DEBUG_INFO,"Pmr(%d) disabled\n", Index));
|
} else {
|
DEBUG ((DEBUG_INFO,"Pmr(%d) not enabled\n", Index));
|
}
|
}
|
return ;
|
}
|
|
/**
|
Enable DMAR translation.
|
|
@retval EFI_SUCCESS DMAR translation is enabled.
|
@retval EFI_DEVICE_ERROR DMAR translation is not enabled.
|
**/
|
EFI_STATUS
|
EnableDmar (
|
VOID
|
)
|
{
|
UINTN Index;
|
UINT32 Reg32;
|
|
for (Index = 0; Index < mVtdUnitNumber; Index++) {
|
DEBUG((DEBUG_INFO, ">>>>>>EnableDmar() for engine [%d] \n", Index));
|
|
if (mVtdUnitInformation[Index].ExtRootEntryTable != NULL) {
|
DEBUG((DEBUG_INFO, "ExtRootEntryTable 0x%x \n", mVtdUnitInformation[Index].ExtRootEntryTable));
|
MmioWrite64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_RTADDR_REG, (UINT64)(UINTN)mVtdUnitInformation[Index].ExtRootEntryTable | BIT11);
|
} else {
|
DEBUG((DEBUG_INFO, "RootEntryTable 0x%x \n", mVtdUnitInformation[Index].RootEntryTable));
|
MmioWrite64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_RTADDR_REG, (UINT64)(UINTN)mVtdUnitInformation[Index].RootEntryTable);
|
}
|
|
Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
|
MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG, Reg32 | B_GMCD_REG_SRTP);
|
|
DEBUG((DEBUG_INFO, "EnableDmar: waiting for RTPS bit to be set... \n"));
|
do {
|
Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
|
} while((Reg32 & B_GSTS_REG_RTPS) == 0);
|
|
//
|
// Init DMAr Fault Event and Data registers
|
//
|
Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_FEDATA_REG);
|
|
//
|
// Write Buffer Flush before invalidation
|
//
|
FlushWriteBuffer (Index);
|
|
//
|
// Invalidate the context cache
|
//
|
InvalidateContextCache (Index);
|
|
//
|
// Invalidate the IOTLB cache
|
//
|
InvalidateIOTLB (Index);
|
|
//
|
// Enable VTd
|
//
|
Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
|
MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG, Reg32 | B_GMCD_REG_TE);
|
DEBUG((DEBUG_INFO, "EnableDmar: Waiting B_GSTS_REG_TE ...\n"));
|
do {
|
Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
|
} while ((Reg32 & B_GSTS_REG_TE) == 0);
|
|
DEBUG ((DEBUG_INFO,"VTD (%d) enabled!<<<<<<\n",Index));
|
}
|
|
//
|
// Need disable PMR, since we already setup translation table.
|
//
|
DisablePmr ();
|
|
mVtdEnabled = TRUE;
|
|
return EFI_SUCCESS;
|
}
|
|
/**
|
Disable DMAR translation.
|
|
@retval EFI_SUCCESS DMAR translation is disabled.
|
@retval EFI_DEVICE_ERROR DMAR translation is not disabled.
|
**/
|
EFI_STATUS
|
DisableDmar (
|
VOID
|
)
|
{
|
UINTN Index;
|
UINTN SubIndex;
|
UINT32 Reg32;
|
UINT32 Status;
|
UINT32 Command;
|
|
for (Index = 0; Index < mVtdUnitNumber; Index++) {
|
DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%d] \n", Index));
|
|
//
|
// Write Buffer Flush before invalidation
|
//
|
FlushWriteBuffer (Index);
|
|
//
|
// Disable Dmar
|
//
|
//
|
// Set TE (Translation Enable: BIT31) of Global command register to zero
|
//
|
Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
|
Status = (Reg32 & 0x96FFFFFF); // Reset the one-shot bits
|
Command = (Status & ~B_GMCD_REG_TE);
|
MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG, Command);
|
|
//
|
// Poll on TE Status bit of Global status register to become zero
|
//
|
do {
|
Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
|
} while ((Reg32 & B_GSTS_REG_TE) == B_GSTS_REG_TE);
|
|
//
|
// Set SRTP (Set Root Table Pointer: BIT30) of Global command register in order to update the root table pointerDisable VTd
|
//
|
Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
|
Status = (Reg32 & 0x96FFFFFF); // Reset the one-shot bits
|
Command = (Status | B_GMCD_REG_SRTP);
|
MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG, Command);
|
|
do {
|
Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
|
} while((Reg32 & B_GSTS_REG_RTPS) == 0);
|
|
Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
|
DEBUG((DEBUG_INFO, "DisableDmar: GSTS_REG - 0x%08x\n", Reg32));
|
|
DEBUG ((DEBUG_INFO,"VTD (%d) Disabled!<<<<<<\n",Index));
|
|
DisableQueuedInvalidationInterface(Index);
|
}
|
|
mVtdEnabled = FALSE;
|
|
for (Index = 0; Index < mVtdUnitNumber; Index++) {
|
DEBUG((DEBUG_INFO, "engine [%d] access\n", Index));
|
for (SubIndex = 0; SubIndex < mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceDataNumber; SubIndex++) {
|
DEBUG ((DEBUG_INFO, " PCI S%04X B%02x D%02x F%02x - %d\n",
|
mVtdUnitInformation[Index].Segment,
|
mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceData[Index].PciSourceId.Bits.Bus,
|
mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceData[Index].PciSourceId.Bits.Device,
|
mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceData[Index].PciSourceId.Bits.Function,
|
mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceData[Index].AccessCount
|
));
|
}
|
}
|
|
return EFI_SUCCESS;
|
}
|
|
/**
|
Dump VTd version registers.
|
|
@param[in] VerReg The version register.
|
**/
|
VOID
|
DumpVtdVerRegs (
|
IN VTD_VER_REG *VerReg
|
)
|
{
|
DEBUG ((DEBUG_INFO, " VerReg:\n", VerReg->Uint32));
|
DEBUG ((DEBUG_INFO, " Major - 0x%x\n", VerReg->Bits.Major));
|
DEBUG ((DEBUG_INFO, " Minor - 0x%x\n", VerReg->Bits.Minor));
|
}
|
|
/**
|
Dump VTd capability registers.
|
|
@param[in] CapReg The capability register.
|
**/
|
VOID
|
DumpVtdCapRegs (
|
IN VTD_CAP_REG *CapReg
|
)
|
{
|
DEBUG((DEBUG_INFO, " CapReg:\n", CapReg->Uint64));
|
DEBUG((DEBUG_INFO, " ND - 0x%x\n", CapReg->Bits.ND));
|
DEBUG((DEBUG_INFO, " AFL - 0x%x\n", CapReg->Bits.AFL));
|
DEBUG((DEBUG_INFO, " RWBF - 0x%x\n", CapReg->Bits.RWBF));
|
DEBUG((DEBUG_INFO, " PLMR - 0x%x\n", CapReg->Bits.PLMR));
|
DEBUG((DEBUG_INFO, " PHMR - 0x%x\n", CapReg->Bits.PHMR));
|
DEBUG((DEBUG_INFO, " CM - 0x%x\n", CapReg->Bits.CM));
|
DEBUG((DEBUG_INFO, " SAGAW - 0x%x\n", CapReg->Bits.SAGAW));
|
DEBUG((DEBUG_INFO, " MGAW - 0x%x\n", CapReg->Bits.MGAW));
|
DEBUG((DEBUG_INFO, " ZLR - 0x%x\n", CapReg->Bits.ZLR));
|
DEBUG((DEBUG_INFO, " FRO - 0x%x\n", CapReg->Bits.FRO));
|
DEBUG((DEBUG_INFO, " SLLPS - 0x%x\n", CapReg->Bits.SLLPS));
|
DEBUG((DEBUG_INFO, " PSI - 0x%x\n", CapReg->Bits.PSI));
|
DEBUG((DEBUG_INFO, " NFR - 0x%x\n", CapReg->Bits.NFR));
|
DEBUG((DEBUG_INFO, " MAMV - 0x%x\n", CapReg->Bits.MAMV));
|
DEBUG((DEBUG_INFO, " DWD - 0x%x\n", CapReg->Bits.DWD));
|
DEBUG((DEBUG_INFO, " DRD - 0x%x\n", CapReg->Bits.DRD));
|
DEBUG((DEBUG_INFO, " FL1GP - 0x%x\n", CapReg->Bits.FL1GP));
|
DEBUG((DEBUG_INFO, " PI - 0x%x\n", CapReg->Bits.PI));
|
}
|
|
/**
|
Dump VTd extended capability registers.
|
|
@param[in] ECapReg The extended capability register.
|
**/
|
VOID
|
DumpVtdECapRegs (
|
IN VTD_ECAP_REG *ECapReg
|
)
|
{
|
DEBUG((DEBUG_INFO, " ECapReg:\n", ECapReg->Uint64));
|
DEBUG((DEBUG_INFO, " C - 0x%x\n", ECapReg->Bits.C));
|
DEBUG((DEBUG_INFO, " QI - 0x%x\n", ECapReg->Bits.QI));
|
DEBUG((DEBUG_INFO, " DT - 0x%x\n", ECapReg->Bits.DT));
|
DEBUG((DEBUG_INFO, " IR - 0x%x\n", ECapReg->Bits.IR));
|
DEBUG((DEBUG_INFO, " EIM - 0x%x\n", ECapReg->Bits.EIM));
|
DEBUG((DEBUG_INFO, " PT - 0x%x\n", ECapReg->Bits.PT));
|
DEBUG((DEBUG_INFO, " SC - 0x%x\n", ECapReg->Bits.SC));
|
DEBUG((DEBUG_INFO, " IRO - 0x%x\n", ECapReg->Bits.IRO));
|
DEBUG((DEBUG_INFO, " MHMV - 0x%x\n", ECapReg->Bits.MHMV));
|
DEBUG((DEBUG_INFO, " ECS - 0x%x\n", ECapReg->Bits.ECS));
|
DEBUG((DEBUG_INFO, " MTS - 0x%x\n", ECapReg->Bits.MTS));
|
DEBUG((DEBUG_INFO, " NEST - 0x%x\n", ECapReg->Bits.NEST));
|
DEBUG((DEBUG_INFO, " DIS - 0x%x\n", ECapReg->Bits.DIS));
|
DEBUG((DEBUG_INFO, " PASID - 0x%x\n", ECapReg->Bits.PASID));
|
DEBUG((DEBUG_INFO, " PRS - 0x%x\n", ECapReg->Bits.PRS));
|
DEBUG((DEBUG_INFO, " ERS - 0x%x\n", ECapReg->Bits.ERS));
|
DEBUG((DEBUG_INFO, " SRS - 0x%x\n", ECapReg->Bits.SRS));
|
DEBUG((DEBUG_INFO, " NWFS - 0x%x\n", ECapReg->Bits.NWFS));
|
DEBUG((DEBUG_INFO, " EAFS - 0x%x\n", ECapReg->Bits.EAFS));
|
DEBUG((DEBUG_INFO, " PSS - 0x%x\n", ECapReg->Bits.PSS));
|
}
|
|
/**
|
Dump VTd registers.
|
|
@param[in] VtdIndex The index of VTd engine.
|
**/
|
VOID
|
DumpVtdRegs (
|
IN UINTN VtdIndex
|
)
|
{
|
UINTN Index;
|
UINT64 Reg64;
|
VTD_FRCD_REG FrcdReg;
|
VTD_CAP_REG CapReg;
|
UINT32 Reg32;
|
VTD_SOURCE_ID SourceId;
|
|
DEBUG((DEBUG_INFO, "#### DumpVtdRegs(%d) Begin ####\n", VtdIndex));
|
|
Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_VER_REG);
|
DEBUG((DEBUG_INFO, " VER_REG - 0x%08x\n", Reg32));
|
|
CapReg.Uint64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CAP_REG);
|
DEBUG((DEBUG_INFO, " CAP_REG - 0x%016lx\n", CapReg.Uint64));
|
|
Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_ECAP_REG);
|
DEBUG((DEBUG_INFO, " ECAP_REG - 0x%016lx\n", Reg64));
|
|
Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GSTS_REG);
|
DEBUG((DEBUG_INFO, " GSTS_REG - 0x%08x \n", Reg32));
|
|
Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_RTADDR_REG);
|
DEBUG((DEBUG_INFO, " RTADDR_REG - 0x%016lx\n", Reg64));
|
|
Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CCMD_REG);
|
DEBUG((DEBUG_INFO, " CCMD_REG - 0x%016lx\n", Reg64));
|
|
Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FSTS_REG);
|
DEBUG((DEBUG_INFO, " FSTS_REG - 0x%08x\n", Reg32));
|
|
Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FECTL_REG);
|
DEBUG((DEBUG_INFO, " FECTL_REG - 0x%08x\n", Reg32));
|
|
Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FEDATA_REG);
|
DEBUG((DEBUG_INFO, " FEDATA_REG - 0x%08x\n", Reg32));
|
|
Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FEADDR_REG);
|
DEBUG((DEBUG_INFO, " FEADDR_REG - 0x%08x\n",Reg32));
|
|
Reg32 = MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_FEUADDR_REG);
|
DEBUG((DEBUG_INFO, " FEUADDR_REG - 0x%08x\n",Reg32));
|
|
for (Index = 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) {
|
FrcdReg.Uint64[0] = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG));
|
FrcdReg.Uint64[1] = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)));
|
DEBUG((DEBUG_INFO, " FRCD_REG[%d] - 0x%016lx %016lx\n", Index, FrcdReg.Uint64[1], FrcdReg.Uint64[0]));
|
if (FrcdReg.Uint64[1] != 0 || FrcdReg.Uint64[0] != 0) {
|
DEBUG((DEBUG_INFO, " Fault Info - 0x%016lx\n", VTD_64BITS_ADDRESS(FrcdReg.Bits.FILo, FrcdReg.Bits.FIHi)));
|
SourceId.Uint16 = (UINT16)FrcdReg.Bits.SID;
|
DEBUG((DEBUG_INFO, " Source - B%02x D%02x F%02x\n", SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));
|
DEBUG((DEBUG_INFO, " Type - %x (%a)\n", FrcdReg.Bits.T, FrcdReg.Bits.T ? "read" : "write"));
|
DEBUG((DEBUG_INFO, " Reason - %x (Refer to VTd Spec, Appendix A)\n", FrcdReg.Bits.FR));
|
}
|
}
|
|
Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IVA_REG);
|
DEBUG((DEBUG_INFO, " IVA_REG - 0x%016lx\n",Reg64));
|
|
Reg64 = MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG);
|
DEBUG((DEBUG_INFO, " IOTLB_REG - 0x%016lx\n",Reg64));
|
|
DEBUG((DEBUG_INFO, "#### DumpVtdRegs(%d) End ####\n", VtdIndex));
|
}
|
|
/**
|
Dump VTd registers for all VTd engine.
|
**/
|
VOID
|
DumpVtdRegsAll (
|
VOID
|
)
|
{
|
UINTN Num;
|
|
for (Num = 0; Num < mVtdUnitNumber; Num++) {
|
DumpVtdRegs (Num);
|
}
|
}
|
|
/**
|
Dump VTd registers if there is error.
|
**/
|
VOID
|
DumpVtdIfError (
|
VOID
|
)
|
{
|
UINTN Num;
|
UINTN Index;
|
VTD_FRCD_REG FrcdReg;
|
VTD_CAP_REG CapReg;
|
UINT32 Reg32;
|
BOOLEAN HasError;
|
|
for (Num = 0; Num < mVtdUnitNumber; Num++) {
|
HasError = FALSE;
|
Reg32 = MmioRead32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FSTS_REG);
|
if (Reg32 != 0) {
|
HasError = TRUE;
|
}
|
Reg32 = MmioRead32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FECTL_REG);
|
if ((Reg32 & BIT30) != 0) {
|
HasError = TRUE;
|
}
|
|
CapReg.Uint64 = MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_CAP_REG);
|
for (Index = 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) {
|
FrcdReg.Uint64[0] = MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG));
|
FrcdReg.Uint64[1] = MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)));
|
if (FrcdReg.Bits.F != 0) {
|
HasError = TRUE;
|
}
|
}
|
|
if (HasError) {
|
REPORT_STATUS_CODE (EFI_ERROR_CODE, PcdGet32 (PcdErrorCodeVTdError));
|
DEBUG((DEBUG_INFO, "\n#### ERROR ####\n"));
|
DumpVtdRegs (Num);
|
DEBUG((DEBUG_INFO, "#### ERROR ####\n\n"));
|
//
|
// Clear
|
//
|
for (Index = 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) {
|
FrcdReg.Uint64[1] = MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)));
|
if (FrcdReg.Bits.F != 0) {
|
//
|
// Software writes the value read from this field (F) to Clear it.
|
//
|
MmioWrite64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)), FrcdReg.Uint64[1]);
|
}
|
}
|
MmioWrite32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FSTS_REG, MmioRead32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FSTS_REG));
|
}
|
}
|
}
|
