/** @file
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SA Platform Lib implementation.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "SaPlatformLibrary.h"
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#include <Library/PciSegmentLib.h>
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#include <SaRegs.h>
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#include <Library/CpuPlatformLib.h>
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/**
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Determine if PCH Link is DMI/OPI
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@param[in] CpuModel CPU model
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@retval TRUE DMI
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@retval FALSE OPI
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**/
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BOOLEAN
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IsPchLinkDmi (
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IN CPU_FAMILY CpuModel
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)
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{
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if ((CpuModel == EnumCpuCflDtHalo) || (CpuModel == EnumCpuCnlDtHalo)) {
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return TRUE; // DMI
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}
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return FALSE; // OPI
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}
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/**
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Returns the number of DMI lanes for current CPU
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@retval UINT8
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**/
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UINT8
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GetMaxDmiLanes (
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)
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{
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return SA_DMI_CFL_MAX_LANE;
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}
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/**
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Returns the number of DMI bundles for current CPU
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@retval UINT8
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**/
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UINT8
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GetMaxDmiBundles (
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)
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{
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return SA_DMI_CFL_MAX_BUNDLE;
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}
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/**
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Returns the function numbers for current CPU
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@retval UINT8
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**/
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UINT8
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GetMaxPegFuncs (
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)
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{
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if (GetCpuFamily() == EnumCpuCnlDtHalo) {
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return SA_PEG_CNL_H_MAX_FUN;
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} else {
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return SA_PEG_NON_CNL_H_MAX_FUN;
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}
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}
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/**
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Returns the number of PEG lanes for current CPU
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@retval UINT8
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**/
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UINT8
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GetMaxPegLanes (
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)
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{
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if (GetCpuFamily() == EnumCpuCnlDtHalo) {
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return SA_PEG_CNL_H_MAX_LANE;
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} else {
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return SA_PEG_NON_CNL_H_MAX_LANE;
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}
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}
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/**
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Returns the number of PEG bundles for current CPU
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@retval UINT8
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**/
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UINT8
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GetMaxPegBundles (
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)
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{
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if (GetCpuFamily() == EnumCpuCnlDtHalo) {
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return SA_PEG_CNL_H_MAX_BUNDLE;
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} else {
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return SA_PEG_NON_CNL_H_MAX_BUNDLE;
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}
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}
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/**
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Checks if PEG port is present
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@retval TRUE PEG is presented
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@retval FALSE PEG is not presented
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**/
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BOOLEAN
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IsPegPresent (
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VOID
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)
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{
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UINT64 PegBaseAddress;
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PegBaseAddress = PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_PEG_BUS_NUM, SA_PEG_DEV_NUM, 0, 0);
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if (PciSegmentRead16 (PegBaseAddress) != 0xFFFF) {
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return TRUE;
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}
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return FALSE;
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}
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