/** @file
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Register names for IGD block
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<b>Conventions</b>:
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- Prefixes:
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- Definitions beginning with "R_" are registers
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- Definitions beginning with "B_" are bits within registers
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- Definitions beginning with "V_" are meaningful values of bits within the registers
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- Definitions beginning with "S_" are register sizes
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- Definitions beginning with "N_" are the bit position
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- In general, SA registers are denoted by "_SA_" in register names
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- Registers / bits that are different between SA generations are denoted by
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"_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_"
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- Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
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at the end of the register/bit names
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- Registers / bits of new devices introduced in a SA generation will be just named
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as "_SA_" without [generation_name] inserted.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _SA_REGS_IGD_H_
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#define _SA_REGS_IGD_H_
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///
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/// Device 2 Register Equates
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///
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//
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// The following equates must be reviewed and revised when the specification is ready.
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//
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#define SA_IGD_BUS 0x00
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#define SA_IGD_DEV 0x02
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#define SA_IGD_FUN_0 0x00
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#define SA_IGD_DEV_FUN (SA_IGD_DEV << 3)
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#define SA_IGD_BUS_DEV_FUN (SA_MC_BUS << 8) + SA_IGD_DEV_FUN
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#define V_SA_IGD_VID 0x8086
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#define SA_GT_APERTURE_SIZE_256MB 1 ///< 256MB is the recommanded GT Aperture Size as per BWG.
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#define V_SA_PCI_DEV_2_GT2_CFL_ULT_1_ID 0x3EA0 ///< Dev2 CFL-U GT2
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#define V_SA_PCI_DEV_2_GT1_CFL_ULT_1_ID 0x3EA1 ///< Dev2 CFL-U GT1
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#define R_SA_IGD_VID 0x00
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#define R_SA_IGD_DID 0x02
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#define R_SA_IGD_CMD 0x04
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#define R_SA_IGD_SWSCI_OFFSET 0x00E8
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#define R_SA_IGD_ASLS_OFFSET 0x00FC ///< ASL Storage
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#endif
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