/** @file
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Register names for Host Bridge block
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<b>Conventions</b>:
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- Prefixes:
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- Definitions beginning with "R_" are registers
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- Definitions beginning with "B_" are bits within registers
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- Definitions beginning with "V_" are meaningful values of bits within the registers
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- Definitions beginning with "S_" are register sizes
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- Definitions beginning with "N_" are the bit position
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- In general, SA registers are denoted by "_SA_" in register names
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- Registers / bits that are different between SA generations are denoted by
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"_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_"
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- Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
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at the end of the register/bit names
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- Registers / bits of new devices introduced in a SA generation will be just named
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as "_SA_" without [generation_name] inserted.
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Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _SA_REGS_HOST_BRIDGE_H_
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#define _SA_REGS_HOST_BRIDGE_H_
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//
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// DEVICE 0 (Memory Controller Hub)
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//
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#define SA_MC_BUS 0x00
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#define SA_MC_DEV 0x00
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#define SA_MC_FUN 0x00
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#define V_SA_MC_VID 0x8086
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#define R_SA_MC_DEVICE_ID 0x02
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#define R_SA_MC_CAPID0_B 0xE8
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///
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/// Maximum number of SDRAM channels supported by the memory controller
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///
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#define SA_MC_MAX_CHANNELS 2
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///
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/// Maximum number of DIMM sockets supported by each channel
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///
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#define SA_MC_MAX_SLOTS 2
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///
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/// Maximum number of sides supported per DIMM
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///
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#define SA_MC_MAX_SIDES 2
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///
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/// Maximum number of DIMM sockets supported by the memory controller
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///
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#define SA_MC_MAX_SOCKETS (SA_MC_MAX_CHANNELS * SA_MC_MAX_SLOTS)
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///
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/// Maximum number of rows supported by the memory controller
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///
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#define SA_MC_MAX_RANKS (SA_MC_MAX_SOCKETS * SA_MC_MAX_SIDES)
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///
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/// Maximum number of rows supported by the memory controller
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///
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#define SA_MC_MAX_ROWS (SA_MC_MAX_SIDES * SA_MC_MAX_SOCKETS)
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///
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/// Maximum memory supported by the memory controller
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/// 4 GB in terms of KB
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///
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#define SA_MC_MAX_MEM_CAPACITY (4 * 1024 * 1024)
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///
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/// Define the maximum number of data bytes on a system with no ECC memory support.
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///
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#define SA_MC_MAX_BYTES_NO_ECC (8)
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///
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/// Define the maximum number of SPD data bytes on a DIMM.
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///
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#define SA_MC_MAX_SPD_SIZE (512)
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//
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// Maximum DMI lanes and bundles supported (x8 and 4 lanes)
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//
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#define SA_DMI_MAX_LANE 0x04
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#define SA_DMI_MAX_BUNDLE 0x02
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#define SA_DMI_CFL_MAX_LANE 0x04
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#define SA_DMI_CFL_MAX_BUNDLE 0x02
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//
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// KabyLake CPU Mobile SA Device IDs B0:D0:F0
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//
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#define V_SA_DEVICE_ID_KBL_MB_ULT_1 0x5904 ///< Kabylake Ult (OPI) (2+1F/1.5F/2F/3/3E) Mobile SA DID
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//
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// KabyLake CPU Halo SA Device IDs B0:D0:F0
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//
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#define V_SA_DEVICE_ID_KBL_HALO_2 0x5910 ///< Kabylake Halo (4+2/4E/3FE) SA DID
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//
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// KabyLake CPU Desktop SA Device IDs B0:D0:F0
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//
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#define V_SA_DEVICE_ID_KBL_DT_2 0x591F ///< Kabylake Desktop (4+1.5F/2/4) SA DID
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//
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// KabyLake CPU Server SA Device IDs B0:D0:F0
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//
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#define V_SA_DEVICE_ID_KBL_SVR_2 0x5918 ///< Kabylake Server (4+1/2/4E) SA DID
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//
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// CoffeeLake CPU Mobile SA Device IDs B0:D0:F0
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//
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#define V_SA_DEVICE_ID_CFL_ULT_1 0x3ED0 ///< CoffeeLake Mobile (CFL-U 4+3e) SA DID
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#define V_SA_DEVICE_ID_CFL_ULT_2 0x3ECC ///< CoffeeLake Mobile (CFL-U 2+3e) SA DID
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#define V_SA_DEVICE_ID_CFL_ULT_3 0x3E34 ///< CoffeeLake Mobile (CFL-U 4+(1 or 2)) SA DID
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#define V_SA_DEVICE_ID_CFL_ULT_4 0x3E35 ///< CoffeeLake Mobile (CFL-U 2+(1 or 2)) SA DID
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#define V_SA_DEVICE_ID_CFL_ULT_6 0x3ECC ///< CoffeeLake Mobile (CFL-U 2+3e) SA DID
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#define V_SA_DEVICE_ID_CML_ULT_1 0x9B51 ///< CometLake (CML-U 6+2) SA DID
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#define V_SA_DEVICE_ID_CML_ULT_2 0x9B61 ///< CometLake (CML-U 4+2) SA DID
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#define V_SA_DEVICE_ID_CML_ULT_3 0x9B71 ///< CometLake (CML-U 2+2) SA DID
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//
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// CoffeeLake CPU Desktop SA Device IDs B0:D0:F0
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//
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#define V_SA_DEVICE_ID_CFL_DT_1 0x3EC2 ///< CoffeeLake Desktop (6+2) SA DID
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#define V_SA_DEVICE_ID_CFL_DT_2 0x3E1F ///< CoffeeLake Desktop (4+2) SA DID
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#define V_SA_DEVICE_ID_CFL_DT_3 0x3E0F ///< CoffeeLake Desktop (2+2) SA DID
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#define V_SA_DEVICE_ID_CFL_DT_4 0x3E30 ///< CoffeeLake Desktop (8+2) SA DID
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//
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// CoffeeLake CPU Halo SA Device IDs B0:D0:F0
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//
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#define V_SA_DEVICE_ID_CFL_HALO_1 0x3EC4 ///< CoffeeLake Halo (6+2) SA DID
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#define V_SA_DEVICE_ID_CFL_HALO_2 0x3E10 ///< CoffeeLake Halo (4+2) SA DID
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#define V_SA_DEVICE_ID_CFL_HALO_3 0x3E20 ///< CoffeeLake Halo (8+2) SA DID
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//
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// CoffeeLake CPU WS SA Device IDs B0:D0:F0
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//
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#define V_SA_DEVICE_ID_CFL_WS_1 0x3EC6 ///< CoffeeLake WorkStation (6+2) SA DID
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#define V_SA_DEVICE_ID_CFL_WS_2 0x3E18 ///< CoffeeLake WrokStation (4+2) SA DID
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#define V_SA_DEVICE_ID_CFL_WS_3 0x3E31 ///< CoffeeLake WrokStation (8+2) SA DID
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//
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// CPU Server SA Device IDs B0:D0:F0
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//
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#define V_SA_DEVICE_ID_CFL_SVR_1 0x3ECA ///< CoffeeLake Server (6+0) SA DID
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#define V_SA_DEVICE_ID_CFL_SVR_2 0x3E32 ///< CoffeeLake Server (8+0) SA DID
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#define V_SA_DEVICE_ID_CFL_SVR_3 0x3E33 ///< CoffeeLake Server (4+0) SA DID
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/**
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<b>Description</b>:
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- This is the base address for the Host Memory Mapped Configuration space. There is no physical memory within this 32KB window that can be addressed. The 32KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space. On reset, the Host MMIO Memory Mapped Configuation space is disabled and must be enabled by writing a 1 to MCHBAREN [Dev 0, offset48h, bit 0].
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- All the bits in this register are locked in LT mode.
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- The register space contains memory control, initialization, timing, and buffer strength registers; clocking registers; and power and thermal management registers.
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**/
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#define R_SA_MCHBAR (0x48)
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/**
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<b>Description</b>:
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- All the bits in this register are LT lockable.
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**/
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#define R_SA_GGC (0x50)
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#define N_SA_GGC_GMS_OFFSET (0x8)
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#define B_SA_GGC_GMS_MASK (0xff00)
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#define N_SA_GGC_GGMS_OFFSET (0x6)
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#define B_SA_GGC_GGMS_MASK (0xc0)
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#define V_SA_GGC_GGMS_8MB 3
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/**
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Description:
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- Allows for enabling/disabling of PCI devices and functions that are within the CPU package. The table below the bit definitions describes the behavior of all combinations of transactions to devices controlled by this register.
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All the bits in this register are LT Lockable.
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**/
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#define R_SA_DEVEN (0x54)
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#define B_SA_DEVEN_D2EN_MASK (0x10)
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/**
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Description:
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This is the base address for the PCI Express configuration space. This window of addresses contains the 4KB of configuration space for each PCI Express device that can potentially be part of the PCI Express Hierarchy associated with the Uncore. There is no actual physical memory within this window of up to 256MB that can be addressed. The actual size of this range is determined by a field in this register.
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Each PCI Express Hierarchy requires a PCI Express BASE register. The Uncore supports one PCI Express Hierarchy. The region reserved by this register does not alias to any PCI2.3 compliant memory mapped space. For example, the range reserved for MCHBAR is outside of PCIEXBAR space.
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On reset, this register is disabled and must be enabled by writing a 1 to the enable field in this register. This base address shall be assigned on a boundary consistent with the number of buses (defined by the length field in this register), above TOLUD and still within 39-bit addressable memory space.
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The PCI Express Base Address cannot be less than the maximum address written to the Top of physical memory register (TOLUD). Software must guarantee that these ranges do not overlap with known ranges located above TOLUD.
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Software must ensure that the sum of the length of the enhanced configuration region + TOLUD + any other known ranges reserved above TOLUD is not greater than the 39-bit addessable limit of 512GB. In general, system implementation and the number of PCI/PCI Express/PCI-X buses supported in the hierarchy will dictate the length of the region.
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All the bits in this register are locked in LT mode.
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**/
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#define R_SA_PCIEXBAR (0x60)
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/**
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Description:
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- This register controls the read, write and shadowing attributes of the BIOS range from F_0000h to F_FFFFh. The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768KB to 1MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled via the MTRR register in the core.
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- Two bits are used to specify memory attributes for each memory segment. These bits apply to host accesses to the PAM areas. These attributes are:
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- RE - Read Enable. When RE=1, the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory. Conversely, when RE=0, the host read accesses are directed to DMI.
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- WE - Write Enable. When WE=1, the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory. Conversely, when WE=0, the host read accesses are directed to DMI.
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- The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write or Disabled. For example, if a memory segment has RE=1 and WE=0, the segment is Read Only.
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**/
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#define R_SA_PAM0 (0x80)
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///
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/// Description:
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/// The SMRAMC register controls how accesses to Compatible SMRAM spaces are treated. The Open, Close and Lock bits function only when G_SMRAME bit is set to 1. Also, the Open bit must be reset before the Lock bit is set.
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///
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#define R_SA_SMRAMC (0x88)
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#define B_SA_SMRAMC_D_LCK_MASK (0x10)
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#define B_SA_SMRAMC_D_CLS_MASK (0x20)
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#define B_SA_SMRAMC_D_OPEN_MASK (0x40)
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///
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/// Description:
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/// This register contains the Top of low memory address.
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///
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#define R_SA_TOLUD (0xbc)
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#define R_SA_MC_CAPID0_A_OFFSET 0xE4
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//
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// MCHBAR IO Register Offset Equates
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//
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#define R_SA_MCHBAR_BIOS_RESET_CPL_OFFSET 0x5DA8
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#define V_SA_LTR_MAX_SNOOP_LATENCY_VALUE 0x0846 ///< Intel recommended maximum value for Snoop Latency (70us)
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#define V_SA_LTR_MAX_NON_SNOOP_LATENCY_VALUE 0x0846 ///< Intel recommended maximum value for Non-Snoop Latency (70us)
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///
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/// Vt-d Engine base address.
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///
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#define R_SA_MCHBAR_VTD1_OFFSET 0x5400 ///< HW UNIT1 for IGD
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#define R_SA_MCHBAR_VTD3_OFFSET 0x5410 ///< HW UNIT3 for all other - PEG, USB, SATA etc
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#endif
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