/** @file
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Policy details for miscellaneous configuration in System Agent
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _SA_MISC_PEI_CONFIG_H_
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#define _SA_MISC_PEI_CONFIG_H_
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#pragma pack(push, 1)
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#ifndef SA_MC_MAX_SOCKETS
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#define SA_MC_MAX_SOCKETS 4
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#endif
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#define SA_MISC_PEI_CONFIG_REVISION 1
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///
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/// Subsystem Vendor ID / Subsystem ID
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///
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typedef struct _SA_DEFAULT_SVID_SID{
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UINT16 SubSystemVendorId;
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UINT16 SubSystemId;
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} SA_DEFAULT_SVID_SID;
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/**
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This configuration block is to configure SA Miscellaneous variables during PEI Post-Mem.\n
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<b>Revision 1</b>:
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- Initial version.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
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/**
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Offset 28:0
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This policy is used to control enable or disable System Agent Thermal device (0,4,0).
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The default value is <b>1: TRUE</b> for WHL, and <b>0: FALSE</b> for all other CPU's
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**/
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UINT32 Device4Enable:1;
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/**
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Offset 28:1
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<b>(Test)</b>This policy is used to control enable or disable System Agent Chap device (0,7,0).
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<b>0=FALSE</b>,
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1=TRUE.
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**/
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UINT32 ChapDeviceEnable:1;
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/**
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Offset 28:2
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For Platforms supporting Intel(R) SIPP, this policy is use control enable/disable Compatibility Revision ID (CRID) feature.
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<b>0=FALSE</b>,
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1=TRUE
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**/
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UINT32 CridEnable:1;
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UINT32 SkipPamLock:1; ///< Offset 28:3 :To skip PAM register locking. @note It is still recommended to set PCI Config space B0: D0: F0: Offset 80h[0]=1 in platform code even Silicon code skipped this.\n <b>0=All PAM registers will be locked in Silicon code</b>, 1=Skip lock PAM registers in Silicon code.
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UINT32 EdramTestMode:2; ///< Offset 28:4 :EDRAM Test Mode. For EDRAM stepping - 0- EDRAM SW Disable, 1- EDRAM SW Enable, <b> 2- EDRAM HW Mode</b>
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UINT32 RsvdBits0 :26; ///< Offset 28:7 :Reserved for future use
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} SA_MISC_PEI_CONFIG;
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#pragma pack(pop)
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#endif // _SA_MISC_PEI_CONFIG_H_
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