/** @file
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Initializes Serial IO Controllers.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/S3BootScriptLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/DxeServicesTableLib.h>
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#include "PchInit.h"
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#include <Library/PchSerialIoLib.h>
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#include <Library/DevicePathLib.h>
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#include <IndustryStandard/Pci30.h>
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#include <Register/PchRegsSerialIo.h>
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typedef struct {
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ACPI_HID_DEVICE_PATH RootPort;
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ACPI_EXTENDED_HID_DEVICE_PATH AcpiDev;
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CHAR8 HidString[8];
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CHAR8 UidString;
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CHAR8 CidString;
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EFI_DEVICE_PATH_PROTOCOL End;
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} SERIALIO_DEVICE_PATH;
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#define gPciRootBridge {{ACPI_DEVICE_PATH, ACPI_DP, {(UINT8)(sizeof(ACPI_HID_DEVICE_PATH)), 0}}, EISA_PNP_ID (0x0A03), 0}
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#define gAcpiDev {{ACPI_DEVICE_PATH,ACPI_EXTENDED_DP,{(UINT8)(sizeof(ACPI_EXTENDED_HID_DEVICE_PATH)+SERIALIO_TOTAL_ID_LENGTH),0}},0,0,0}
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#define gEndEntire {END_DEVICE_PATH_TYPE,END_ENTIRE_DEVICE_PATH_SUBTYPE,{END_DEVICE_PATH_LENGTH,0}}
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GLOBAL_REMOVE_IF_UNREFERENCED SERIALIO_DEVICE_PATH gSerialIoPath = {
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gPciRootBridge,
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gAcpiDev,
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"\0\0\0\0\0\0\0",
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'\0',
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'\0',
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gEndEntire
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};
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/**
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Mark memory used by SerialIo devices in ACPI mode as allocated
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@retval EFI_SUCCESS The function completed successfully
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**/
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EFI_STATUS
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AllocateSerialIoMemory (
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VOID
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)
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{
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PCH_SERIAL_IO_CONTROLLER i;
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UINT8 BarNumber;
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UINTN Bar;
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EFI_STATUS Status;
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for (i=0; i<PchSerialIoIndexMax; i++) {
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if (mPchConfigHob->SerialIo.DevMode[i] == PchSerialIoHidden ||
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mPchConfigHob->SerialIo.DevMode[i] == PchSerialIoAcpi) {
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for (BarNumber = 0; BarNumber<=1; BarNumber++) {
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Bar = FindSerialIoBar (i,BarNumber);
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Status = gDS->AddMemorySpace (
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EfiGcdMemoryTypeReserved,
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Bar,
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V_SERIAL_IO_CFG_BAR_SIZE,
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0
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);
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ASSERT_EFI_ERROR (Status);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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Status = gDS->AllocateMemorySpace (
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EfiGcdAllocateAddress,
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EfiGcdMemoryTypeReserved,
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N_SERIAL_IO_CFG_BAR_ALIGNMENT,
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V_SERIAL_IO_CFG_BAR_SIZE,
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&Bar,
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mImageHandle,
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NULL
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);
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ASSERT_EFI_ERROR (Status);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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}
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}
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}
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return EFI_SUCCESS;
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}
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VOID
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CreateSerialIoHandles (
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VOID
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)
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{
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EFI_HANDLE NewHandle;
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EFI_DEVICE_PATH_PROTOCOL *NewPath;
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UINT32 Controller;
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for (Controller = 0; Controller < PchSerialIoIndexMax; Controller++) {
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if (mPchConfigHob->SerialIo.DevMode[Controller] == PchSerialIoAcpi) {
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NewHandle = NULL;
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CopyMem (gSerialIoPath.HidString, GetSerialIoAcpiHid (Controller), SERIALIO_HID_LENGTH);
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NewPath = DuplicateDevicePath ((EFI_DEVICE_PATH_PROTOCOL*)&gSerialIoPath);
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gBS->InstallMultipleProtocolInterfaces (
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&NewHandle,
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&gEfiDevicePathProtocolGuid,
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NewPath,
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NULL );
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}
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}
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}
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/**
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Puts all SerialIo controllers (except UARTs in debug mode) in D3.
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Clears MemoryEnable for all PCI-mode controllers on S3 resume
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**/
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VOID
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ConfigureSerialIoAtS3Resume (
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VOID
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)
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{
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PCH_SERIAL_IO_CONTROLLER Index;
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UINTN PciCfgBase;
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UINT32 Data32;
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for (Index = 0; Index < PchSerialIoIndexMax; Index++) {
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if (mPchConfigHob->SerialIo.DevMode[Index] == PchSerialIoDisabled) {
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if (IsSerialIoFunctionZero (Index)) {
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if (IsSerialIoDeviceEnabled (GetSerialIoDeviceNumber (Index), GetSerialIoFunctionNumber (Index))) {
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PciCfgBase = FindSerialIoBar (Index,1);
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Data32 = MmioRead32 (PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS);
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Data32 |= B_SERIAL_IO_CFG_PME_CTRL_STS_PWR_ST;
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S3BootScriptSaveMemWrite (S3BootScriptWidthUint32, PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS, 1, &Data32);
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}
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}
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continue;
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}
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if ((Index >= PchSerialIoIndexUart0) &&
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(mPchConfigHob->SerialIo.EnableDebugUartAfterPost) &&
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(mPchConfigHob->SerialIo.DebugUartNumber == (UINT32) (Index - PchSerialIoIndexUart0))) {
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continue;
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}
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PciCfgBase = FindSerialIoBar (Index,1);
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Data32 = MmioRead32 (PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS);
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Data32 |= B_SERIAL_IO_CFG_PME_CTRL_STS_PWR_ST;
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S3BootScriptSaveMemWrite (S3BootScriptWidthUint32, PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS, 1, &Data32);
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if (mPchConfigHob->SerialIo.DevMode[Index] == PchSerialIoPci) {
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Data32 = MmioRead32 (PciCfgBase + PCI_COMMAND_OFFSET);
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Data32 &= (UINT32)~(EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_BUS_MASTER);
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S3BootScriptSaveMemWrite (S3BootScriptWidthUint32, PciCfgBase + PCI_COMMAND_OFFSET, 1, &Data32);
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}
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}
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}
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