/** @file
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This is the Common driver that initializes the Intel PCH.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/PciSegmentLib.h>
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#include <Library/TimerLib.h>
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#include <Library/S3BootScriptLib.h>
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#include <Library/HobLib.h>
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#include "PchInit.h"
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#include <PchPolicyCommon.h>
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#include <Private/Library/PchSpiCommonLib.h>
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#include <Private/Library/PmcPrivateLib.h>
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#include <Private/Library/PchDmiLib.h>
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#include <Private/Library/SiScheduleResetLib.h>
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#include <Library/PchCycleDecodingLib.h>
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#include <Library/BiosLockLib.h>
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#include <Library/PchPcrLib.h>
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#include <IndustryStandard/Pci30.h>
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#include <Register/PchRegs.h>
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#include <Register/PchRegsPcr.h>
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#include <Register/PchRegsLpc.h>
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#include <Register/PchRegsSpi.h>
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#include <Register/PchRegsPsth.h>
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#include <Register/PchRegsPmc.h>
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//
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// Module variables
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//
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GLOBAL_REMOVE_IF_UNREFERENCED PCH_CONFIG_HOB *mPchConfigHob;
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GLOBAL_REMOVE_IF_UNREFERENCED SI_CONFIG_HOB_DATA *mSiConfigHobData;
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//
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// EFI_EVENT
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//
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GLOBAL_REMOVE_IF_UNREFERENCED EFI_EVENT mHeciEvent;
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/**
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Common PchInit Module Entry Point
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**/
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VOID
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PchInitEntryPointCommon (
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VOID
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)
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{
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EFI_PEI_HOB_POINTERS HobPtr;
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DEBUG ((DEBUG_INFO, "PchInitEntryPointCommon() Start\n"));
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//
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// Get PCH Config HOB.
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//
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HobPtr.Guid = GetFirstGuidHob (&gPchConfigHobGuid);
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ASSERT (HobPtr.Guid != NULL);
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mPchConfigHob = (PCH_CONFIG_HOB *) GET_GUID_HOB_DATA (HobPtr.Guid);
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//
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// Get Silicon Config data HOB
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//
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HobPtr.Guid = GetFirstGuidHob (&gSiConfigHobGuid);
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ASSERT (HobPtr.Guid != NULL);
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mSiConfigHobData = (SI_CONFIG_HOB_DATA *) GET_GUID_HOB_DATA (HobPtr.Guid);
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DEBUG ((DEBUG_INFO, "PchInitEntryPointCommon() End\n"));
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return;
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}
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/**
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Lock SPI register before boot
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**/
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VOID
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LockSpiConfiguration (
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VOID
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)
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{
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UINTN Index;
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UINT16 Data16;
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UINT16 Data16And;
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UINT16 Data16Or;
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UINT32 Data32;
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UINT32 DlockValue;
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UINT64 PciSpiRegBase;
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UINT32 PchSpiBar0;
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UINT32 Timer;
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PciSpiRegBase = PCI_SEGMENT_LIB_ADDRESS (
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DEFAULT_PCI_SEGMENT_NUMBER_PCH,
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_SPI,
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PCI_FUNCTION_NUMBER_PCH_SPI,
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0
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);
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//
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// Check for SPI controller presence before programming
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//
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if (PciSegmentRead32 (PciSpiRegBase + PCI_VENDOR_ID_OFFSET) == 0xFFFF) {
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return;
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}
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//
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// Make sure SPI BAR0 has fixed address before writing to boot script.
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// The same base address is set in PEI and will be used during resume.
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//
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PchSpiBar0 = PCH_SPI_BASE_ADDRESS;
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PciSegmentAnd8 (PciSpiRegBase + PCI_COMMAND_OFFSET, (UINT8) ~EFI_PCI_COMMAND_MEMORY_SPACE);
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PciSegmentWrite32 (PciSpiRegBase + R_SPI_CFG_BAR0, PchSpiBar0);
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PciSegmentOr8 (PciSpiRegBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
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//
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// Program the Flash Protection Range Register based on policy
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//
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DlockValue = MmioRead32 (PchSpiBar0 + R_SPI_MEM_DLOCK);
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for (Index = 0; Index < PCH_FLASH_PROTECTED_RANGES; ++Index) {
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if ((mPchConfigHob->ProtectRange[Index].WriteProtectionEnable ||
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mPchConfigHob->ProtectRange[Index].ReadProtectionEnable) != TRUE) {
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continue;
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}
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//
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// Proceed to program the register after ensure it is enabled
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//
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Data32 = 0;
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Data32 |= (mPchConfigHob->ProtectRange[Index].WriteProtectionEnable == TRUE) ? B_SPI_MEM_PRX_WPE : 0;
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Data32 |= (mPchConfigHob->ProtectRange[Index].ReadProtectionEnable == TRUE) ? B_SPI_MEM_PRX_RPE : 0;
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Data32 |= ((UINT32) mPchConfigHob->ProtectRange[Index].ProtectedRangeLimit << N_SPI_MEM_PRX_PRL) & B_SPI_MEM_PRX_PRL_MASK;
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Data32 |= ((UINT32) mPchConfigHob->ProtectRange[Index].ProtectedRangeBase << N_SPI_MEM_PRX_PRB) & B_SPI_MEM_PRX_PRB_MASK;
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DEBUG ((DEBUG_INFO, "Protected range %d: 0x%08x \n", Index, Data32));
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DlockValue |= (UINT32) (B_SPI_MEM_DLOCK_PR0LOCKDN << Index);
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MmioWrite32 ((UINTN) (PchSpiBar0 + (R_SPI_MEM_PR0 + (Index * S_SPI_MEM_PRX))), Data32);
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S3BootScriptSaveMemWrite (
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S3BootScriptWidthUint32,
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(UINTN) (PchSpiBar0 + (R_SPI_MEM_PR0 + (Index * S_SPI_MEM_PRX))),
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1,
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(VOID *) (UINTN) (PchSpiBar0 + (R_SPI_MEM_PR0 + (Index * S_SPI_MEM_PRX)))
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);
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}
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//
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// Program DLOCK register
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//
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MmioWrite32 ((UINTN) (PchSpiBar0 + R_SPI_MEM_DLOCK), DlockValue);
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S3BootScriptSaveMemWrite (
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S3BootScriptWidthUint32,
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(UINTN) (PchSpiBar0 + R_SPI_MEM_DLOCK),
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1,
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(VOID *) (UINTN) (PchSpiBar0 + R_SPI_MEM_DLOCK)
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);
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///
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/// PCH BIOS Spec Section 3.6 Flash Security Recommendation
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/// In PCH SPI controller the BIOS should set the Flash Configuration Lock-Down bit
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/// (SPI_BAR0 + 04[15]) at end of post. When set to 1, those Flash Program Registers
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/// that are locked down by this FLOCKDN bit cannot be written.
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/// Please refer to the EDS for which program registers are impacted.
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/// Additionally BIOS must program SPI_BAR0 + 0x04 BIT11 (WRSDIS) to disable Write Status in HW sequencing
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///
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//
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// Ensure there is no pending SPI trasaction before setting lock bits
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//
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Timer = 0;
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while (MmioRead16 (PchSpiBar0 + R_SPI_MEM_HSFSC) & B_SPI_MEM_HSFSC_SCIP) {
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if (Timer > SPI_WAIT_TIME) {
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//
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// SPI transaction is pending too long at this point, exit with error.
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//
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DEBUG ((DEBUG_ERROR, "SPI Cycle timeout\n"));
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ASSERT (FALSE);
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break;
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}
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MicroSecondDelay (SPI_WAIT_PERIOD);
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Timer += SPI_WAIT_PERIOD;
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}
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Data16And = B_SPI_MEM_HSFSC_SCIP;
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Data16 = 0;
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S3BootScriptSaveMemPoll (
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S3BootScriptWidthUint16,
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PchSpiBar0 + R_SPI_MEM_HSFSC,
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&Data16And,
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&Data16,
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SPI_WAIT_PERIOD,
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SPI_WAIT_TIME / SPI_WAIT_PERIOD
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);
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//
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// Clear any outstanding status
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//
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Data16Or = B_SPI_MEM_HSFSC_SAF_DLE
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| B_SPI_MEM_HSFSC_SAF_ERROR
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| B_SPI_MEM_HSFSC_AEL
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| B_SPI_MEM_HSFSC_FCERR
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| B_SPI_MEM_HSFSC_FDONE;
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Data16And = 0xFFFF;
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MmioAndThenOr16 (PchSpiBar0 + R_SPI_MEM_HSFSC, Data16And, Data16Or);
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S3BootScriptSaveMemReadWrite (
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S3BootScriptWidthUint16,
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PchSpiBar0 + R_SPI_MEM_HSFSC,
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&Data16Or,
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&Data16And
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);
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//
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// Set WRSDIS
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//
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Data16Or = B_SPI_MEM_HSFSC_WRSDIS;
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Data16And = 0xFFFF;
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MmioAndThenOr16 (PchSpiBar0 + R_SPI_MEM_HSFSC, Data16And, Data16Or);
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S3BootScriptSaveMemReadWrite (
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S3BootScriptWidthUint16,
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PchSpiBar0 + R_SPI_MEM_HSFSC,
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&Data16Or,
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&Data16And
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);
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//
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// Set FLOCKDN
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//
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Data16Or = B_SPI_MEM_HSFSC_FLOCKDN;
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Data16And = 0xFFFF;
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MmioAndThenOr16 (PchSpiBar0 + R_SPI_MEM_HSFSC, Data16And, Data16Or);
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S3BootScriptSaveMemReadWrite (
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S3BootScriptWidthUint16,
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PchSpiBar0 + R_SPI_MEM_HSFSC,
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&Data16Or,
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&Data16And
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);
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///
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/// SPI Flash Programming Guide Section 5.5.2 Vendor Component Lock
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/// It is strongly recommended that BIOS sets the Vendor Component Lock (VCL) bits. VCL applies
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/// the lock to both VSCC0 and VSCC1 even if VSCC0 is not used. Without the VCL bits set, it is
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/// possible to make Host/GbE VSCC register(s) changes in that can cause undesired host and
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/// integrated GbE Serial Flash functionality.
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///
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MmioOr32 ((UINTN) (PchSpiBar0 + R_SPI_MEM_SFDP0_VSCC0), B_SPI_MEM_SFDP0_VSCC0_VCL);
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S3BootScriptSaveMemWrite (
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S3BootScriptWidthUint32,
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(UINTN) (PchSpiBar0 + R_SPI_MEM_SFDP0_VSCC0),
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1,
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(VOID *) (UINTN) (PchSpiBar0 + R_SPI_MEM_SFDP0_VSCC0)
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);
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}
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/**
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Process all the lock downs
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**/
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VOID
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ProcessAllLocks (
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VOID
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)
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{
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UINT8 Data8;
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UINT16 Data16And;
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UINT16 Data16Or;
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UINT32 Data32And;
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UINT32 Data32Or;
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UINT64 PciLpcRegBase;
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UINT16 TcoBase;
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UINT64 PciSpiRegBase;
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PciLpcRegBase = PCI_SEGMENT_LIB_ADDRESS (
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DEFAULT_PCI_SEGMENT_NUMBER_PCH,
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_LPC,
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PCI_FUNCTION_NUMBER_PCH_LPC,
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0
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);
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PciSpiRegBase = PCI_SEGMENT_LIB_ADDRESS (
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DEFAULT_PCI_SEGMENT_NUMBER_PCH,
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_SPI,
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PCI_FUNCTION_NUMBER_PCH_SPI,
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0
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);
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PchTcoBaseGet (&TcoBase);
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//
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// Lock function disable (ST and NST PG) register fields.
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//
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PmcLockFunctionDisableConfigWithS3BootScript ();
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///
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/// PCH BWG Additional PCH DMI and OP-DMI Programming Steps
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/// Lock DMI.
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///
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PchDmiSetLockWithS3BootScript ();
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//
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// Lock SPI register before boot.
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//
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LockSpiConfiguration ();
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///
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/// Additional Power Management Programming
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/// Step 3
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/// Lock configuration after stretch and ACPI base programming completed.
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///
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PmcLockSlpSxStretchingPolicyWithS3BootScript ();
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//
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// Set BiosLock.
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//
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if (mPchConfigHob->LockDown.BiosLock == TRUE) {
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BiosLockEnable ();
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}
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///
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/// PCH BIOS Spec Section 3.6 Flash Security Recommendation
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/// BIOS also needs to set the BIOS Interface Lock Down bit in multiple locations
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/// (PCR[DMI] + 274Ch[0], LPC/eSPI PCI offset DCh[7] and SPI PCI offset DCh[7]).
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/// Setting these bits will prevent writes to the Top Swap bit (under their respective locations)
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/// and the Boot BIOS Straps. Enabling this bit will mitigate malicious software
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/// attempts to replace the system BIOS option ROM with its own code.
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///
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if (mPchConfigHob->LockDown.BiosInterface == TRUE) {
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//
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// LPC
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//
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PciSegmentOr8 ((UINT64) (PciLpcRegBase + R_LPC_CFG_BC), (UINT32) B_LPC_CFG_BC_BILD);
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S3BootScriptSaveMemWrite (
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S3BootScriptWidthUint8,
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PcdGet64 (PcdPciExpressBaseAddress) + PciLpcRegBase + R_LPC_CFG_BC,
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1,
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(VOID *) (UINTN) (PcdGet64 (PcdPciExpressBaseAddress) + PciLpcRegBase + R_LPC_CFG_BC)
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);
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//
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// Reads back for posted write to take effect
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//
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Data8 = PciSegmentRead8 ((UINTN) (PciLpcRegBase + R_LPC_CFG_BC));
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S3BootScriptSaveMemPoll (
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S3BootScriptWidthUint8,
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PcdGet64 (PcdPciExpressBaseAddress) + PciLpcRegBase + R_LPC_CFG_BC,
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&Data8, // BitMask
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&Data8, // BitValue
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1, // Duration
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1 // LoopTimes
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);
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//
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// SPI
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//
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PciSegmentOr8 ((UINT64) (PciSpiRegBase + R_SPI_CFG_BC), (UINT32) B_SPI_CFG_BC_BILD);
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S3BootScriptSaveMemWrite (
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S3BootScriptWidthUint8,
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PcdGet64 (PcdPciExpressBaseAddress) + PciSpiRegBase + R_SPI_CFG_BC,
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1,
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(VOID *) (UINTN) (PcdGet64 (PcdPciExpressBaseAddress) + PciSpiRegBase + R_SPI_CFG_BC)
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);
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//
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// Reads back for posted write to take effect
|
//
|
Data8 = PciSegmentRead8 ((UINT64) (PciSpiRegBase + R_SPI_CFG_BC));
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S3BootScriptSaveMemPoll (
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S3BootScriptWidthUint8,
|
PcdGet64 (PcdPciExpressBaseAddress) + PciSpiRegBase + R_SPI_CFG_BC,
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&Data8, // BitMask
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&Data8, // BitValue
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1, // Duration
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1 // LoopTimes
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);
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///
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/// Set BIOS interface Lock-Down
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///
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PchDmiSetBiosLockDownWithS3BootScript ();
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}
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///
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/// PCH BIOS Spec on using RTC RAM
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/// Regardless of BUC.TS being updated or not, BIOS must set RC.BILD bit PCR[RTC] + 3400h[31] before exit
|
/// For Data integrity protection, set RTC Memory locks (Upper 128 Byte Lock and
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/// Lower 128 Byte Lock) at PCR[RTC] + 3400h[4] and PCR[RTC] + 3400h[3].
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/// Note once locked bytes 0x38 - 0x3F in each of the Upper and Lower Byte blocks, respectively,
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/// cannot be unlocked until next reset.
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///
|
Data32And = 0xFFFFFFFF;
|
Data32Or = 0x0;
|
|
if (mPchConfigHob->LockDown.BiosInterface == TRUE) {
|
Data32Or = B_RTC_PCR_CONF_BILD;
|
}
|
if (mPchConfigHob->LockDown.RtcMemoryLock == TRUE) {
|
Data32Or |= (B_RTC_PCR_CONF_UCMOS_LOCK | B_RTC_PCR_CONF_LCMOS_LOCK);
|
}
|
PchPcrAndThenOr32 (
|
PID_RTC_HOST, R_RTC_PCR_CONF,
|
Data32And,
|
Data32Or
|
);
|
PCH_PCR_BOOT_SCRIPT_READ_WRITE (
|
S3BootScriptWidthUint32,
|
PID_RTC_HOST, R_RTC_PCR_CONF,
|
&Data32Or,
|
&Data32And
|
);
|
|
///
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/// Remove access to RTC PCRs
|
///
|
Data32And = (UINT32)~(BIT0);
|
Data32Or = 0;
|
PchPcrAndThenOr32 (
|
PID_RTC_HOST, R_RTC_PCR_PG1_AC_LO,
|
Data32And,
|
Data32Or
|
);
|
PCH_PCR_BOOT_SCRIPT_READ_WRITE (
|
S3BootScriptWidthUint32,
|
PID_RTC_HOST, R_RTC_PCR_PG1_AC_LO,
|
&Data32Or,
|
&Data32And
|
);
|
PchPcrAndThenOr32 (
|
PID_RTC_HOST, R_RTC_PCR_PG1_CP_LO,
|
Data32And,
|
Data32Or
|
);
|
PCH_PCR_BOOT_SCRIPT_READ_WRITE (
|
S3BootScriptWidthUint32,
|
PID_RTC_HOST, R_RTC_PCR_PG1_CP_LO,
|
&Data32Or,
|
&Data32And
|
);
|
|
//
|
// Lock Down TCO
|
//
|
Data16And = 0xFFFF;
|
Data16Or = B_TCO_IO_TCO1_CNT_LOCK;
|
IoOr16 (TcoBase + R_TCO_IO_TCO1_CNT, Data16Or);
|
S3BootScriptSaveIoReadWrite (
|
S3BootScriptWidthUint16,
|
(UINTN) (TcoBase + R_TCO_IO_TCO1_CNT),
|
&Data16Or, // Data to be ORed
|
&Data16And // Data to be ANDed
|
);
|
|
///
|
/// PCH BIOS Spec Section 5.15.1 Additional Chipset Initialization
|
/// Step 1
|
/// Lock PMC Set Strap Message Interface
|
///
|
PmcLockSetStrapMsgInterfaceWithS3BootScript ();
|
//
|
// Lock Down PMC
|
//
|
PmcLockWithS3BootScript ();
|
}
|
|
/**
|
Set eSPI BME bit
|
**/
|
VOID
|
ConfigureEspiBme (
|
VOID
|
)
|
{
|
UINT64 EspiPciBase;
|
|
EspiPciBase = PCI_SEGMENT_LIB_ADDRESS (
|
DEFAULT_PCI_SEGMENT_NUMBER_PCH,
|
DEFAULT_PCI_BUS_NUMBER_PCH,
|
PCI_DEVICE_NUMBER_PCH_LPC,
|
PCI_FUNCTION_NUMBER_PCH_LPC,
|
0
|
);
|
|
if (PciSegmentRead16 (EspiPciBase + PCI_VENDOR_ID_OFFSET) == 0xFFFF) {
|
return;
|
}
|
if ((PciSegmentRead32 (EspiPciBase + R_ESPI_CFG_PCBC) & B_ESPI_CFG_PCBC_ESPI_EN) == 0) {
|
return;
|
}
|
|
//
|
// Refer to PCH BWG.
|
// To enable eSPI bus mastering BIOS must enable BME in eSPI controller
|
// and also set BME bit in the respective slave devices through Configuration
|
// and Capabilities register of each slave using Get_Configuration and Set_Configuration functionality.
|
//
|
// NOTE: The setting is also done in PEI, but might be cleared by PCI bus during PCI enumeration.
|
// Therefore, reeable it after PCI enumeration done.
|
//
|
if (mPchConfigHob->Espi.BmeMasterSlaveEnabled == TRUE) {
|
PciSegmentOr8 (EspiPciBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_BUS_MASTER);
|
}
|
}
|
|
/**
|
Common PCH initialization before Boot Sript Table is closed
|
|
**/
|
VOID
|
PchOnPciEnumCompleteCommon (
|
VOID
|
)
|
{
|
UINT32 Data32Or;
|
UINT32 Data32And;
|
BOOLEAN ResetStatus;
|
|
DEBUG ((DEBUG_INFO, "PchOnPciEnumCompleteCommon() Start\n"));
|
|
if (SiScheduleResetIsRequired ()) {
|
ResetStatus = SiScheduleResetPerformReset ();
|
ASSERT (!ResetStatus);
|
}
|
|
ProcessAllLocks ();
|
|
//
|
// Perform remaining configuration for PCH SATA on End of DXE
|
//
|
ConfigurePchSataOnEndOfDxe ();
|
//
|
// PSTHCTL (0xD00h[2]) = 1, PSTH IOSF Primary Trunk Clock Gating Enable (PSTHIOSFPTCGE)
|
//
|
Data32And = 0xFFFFFFFF;
|
Data32Or = B_PSTH_PCR_PSTHIOSFPTCGE;
|
PchPcrAndThenOr32 (PID_PSTH, R_PSTH_PCR_PSTHCTL, Data32And, Data32Or);
|
PCH_PCR_BOOT_SCRIPT_READ_WRITE (
|
S3BootScriptWidthUint32,
|
PID_PSTH, R_PSTH_PCR_PSTHCTL,
|
&Data32Or,
|
&Data32And
|
);
|
|
//
|
// Set eSPI BME after PCI enumeration
|
//
|
ConfigureEspiBme ();
|
|
///
|
/// Clear Global Reset Status, Power Failure and Host Reset Status bits
|
///
|
PmcClearGlobalResetStatus ();
|
PmcClearPowerFailureStatus ();
|
PmcClearHostResetStatus ();
|
|
DEBUG ((DEBUG_INFO, "PchOnPciEnumCompleteCommon() End\n"));
|
}
|
