/** @file
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PCH PMC Private Library implementation for Cannon Lake PCH.
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All function in this library is available for PEI, DXE, and SMM,
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But do not support UEFI RUNTIME environment call.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Uefi/UefiBaseType.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Private/Library/PmcPrivateLib.h>
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#include <Library/SataLib.h>
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#include <Library/PchInfoLib.h>
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#include <Register/PchRegsPmc.h>
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#include "PmcPrivateLibInternal.h"
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/**
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This function disables Trace Hub by enabling power gating
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**/
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VOID
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PmcDisableTraceHub (
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VOID
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)
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{
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EFI_STATUS Status;
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PMC_IPC_COMMAND_BUFFER Wbuf;
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ZeroMem (&Wbuf, sizeof (PMC_IPC_COMMAND_BUFFER));
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Wbuf.Buf0 = BIT0;
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Status = PmcSendCommand (V_PMC_PWRM_IPC_CMD_COMMAND_NPK_STATE, 0, 4, &Wbuf, NULL);
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ASSERT_EFI_ERROR (Status);
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}
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/**
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This function enables Trace Hub by disabling power gating
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**/
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VOID
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PmcEnableTraceHub (
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VOID
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)
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{
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EFI_STATUS Status;
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PMC_IPC_COMMAND_BUFFER Wbuf;
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ZeroMem (&Wbuf, sizeof (PMC_IPC_COMMAND_BUFFER));
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Wbuf.Buf0 = BIT1;
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Status = PmcSendCommand (V_PMC_PWRM_IPC_CMD_COMMAND_NPK_STATE, 0, 4, &Wbuf, NULL);
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ASSERT_EFI_ERROR (Status);
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}
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/**
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This function is part of PMC init and configures which clock wake signals should
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set the SLOW_RING, SA, FAST_RING_CF and SLOW_RING_CF indication sent up to the CPU/PCH
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**/
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VOID
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PmcInitClockWakeEnable (
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VOID
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)
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{
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UINT32 PchPwrmBase;
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PchPwrmBase = PmcGetPwrmBase ();
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if (IsPchLp () && (PchStepping () < PCH_B0)) {
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///
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/// PWRMBASE + 0x1880 = 0x0
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///
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MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SLOW_RING, 0x0);
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} else {
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///
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/// PWRMBASE + 0x1880 = 0x2F8FBB01
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///
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MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SLOW_RING, 0x2F8FBB01);
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}
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if (IsPchLp ()) {
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if (PchStepping () < PCH_B0) {
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///
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/// PWRMBASE + 0x1884 = 0x0
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///
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MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SLOW_RING2, 0x0);
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} else {
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///
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/// PWRMBASE + 0x1884
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/// PCH-LP: 0x0280C7E1
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///
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MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SLOW_RING2, 0x0280C7E1);
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}
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} else {
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///
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/// PWRMBASE + 0x1884
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/// PCH-H: 0x0280D7E1
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///
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MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SLOW_RING2, 0x0280D7E1);
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}
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if (IsPchLp () && (PchStepping () < PCH_B0)) {
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///
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/// PWRMBASE + 0x1888 = 0x0
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///
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MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SA, 0x0);
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///
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/// PWRMBASE + 0x188C = 0x0
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///
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MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SA2, 0x0);
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} else {
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///
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/// PWRMBASE + 0x1888 = 0x2F8FAB01
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///
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MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SA, 0x2F8FAB01);
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///
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/// PWRMBASE + 0x188C
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/// PCH-LP: 0x0280C7E1
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/// PCH-H: 0x0280D7E1
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///
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if (IsPchLp ()) {
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MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SA2, 0x0280C7E1);
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} else {
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MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SA2, 0x0280D7E1);
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}
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}
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if (IsPchLp () && (PchStepping () < PCH_B0)) {
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///
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/// PWRMBASE + 0x1898 = 0x0
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///
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MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SLOW_RING_CF, 0x0);
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} else {
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///
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/// PWRMBASE + 0x1898 = 0x00018000
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///
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MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SLOW_RING_CF, 0x00018000);
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}
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}
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/**
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This function configures PWRMBASE + 0x1E00 register
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**/
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VOID
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PmcConfigureRegPwrm1E00 (
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VOID
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)
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{
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///
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/// PWRMBASE + 0x1E00[31,30] = 1,1
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/// PWRMBASE + 0x1E00[29] = 0
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/// PWRMBASE + 0x1E00[10:6] = 0
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/// PWRMBASE + 0x1E00[3:0] = 2
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///
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MmioAndThenOr32 (
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PmcGetPwrmBase () + R_PMC_PWRM_1E00,
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(UINT32) ~(BIT29 | (0x1F << 6) | 0xF),
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BIT31 | BIT30 | 2
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);
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}
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/**
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This function configures Misc PM_SYNC events settings
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**/
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VOID
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PmcConfigurePmSyncEventsSettings (
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VOID
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)
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{
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///
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/// PWRMBASE + 0x18C0 = 0x00000A20
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///
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MmioWrite32 (PmcGetPwrmBase () + R_PMC_PWRM_EN_MISC_EVENT, 0x00000A20);
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}
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/**
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This function enables all SerailIo devices.
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Static power gating disabling takes place after Global Reset, G3 or DeepSx transition.
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**/
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VOID
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PmcEnableSerialIo (
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VOID
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)
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{
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//
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// Set PWRMBASE + ST_PG_FDIS_PMC_2
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//
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MmioAnd32 (PmcGetPwrmBase () + R_PMC_PWRM_ST_PG_FDIS_PMC_2, (UINT32)~B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO);
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}
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/**
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This function disables (static power gating) all SerailIo devices.
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For SerialIo controllers they can be power gated only if all of them are to be disabled.
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They cannot be statically power gated separately.
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For static power gating to take place Global Reset, G3 or DeepSx transition must happen.
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**/
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VOID
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PmcStaticDisableSerialIo (
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VOID
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)
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{
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//
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// Set PWRMBASE + ST_PG_FDIS_PMC_2
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//
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MmioOr32 (PmcGetPwrmBase () + R_PMC_PWRM_ST_PG_FDIS_PMC_2, B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO);
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}
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/**
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This function checks if all SerialIo devices are statically disabled (static power gating)
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@retval SerialIo disable state
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**/
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BOOLEAN
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PmcIsSerialIoStaticallyDisabled (
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VOID
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)
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{
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//
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// Check if all SerialIo controllers are statically disabled in PMC
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//
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return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_ST_PG_FDIS_PMC_2) & B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO) == B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO);
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}
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/**
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This function checks if SerialIo device is supported (not disabled by fuse)
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@retval SerialIo support state
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**/
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BOOLEAN
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PmcIsSerialIoSupported (
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VOID
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)
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{
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//
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// Get fuse info from PWRMBASE + FUSE_SS_DIS_RD_2
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//
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return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_FUSE_DIS_RD_2) & B_PMC_PWRM_FUSE_DIS_RD_2_SERIALIO_FUSE_SS_DIS) == 0);
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}
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/**
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This function disables (non-static power gating) SCS eMMC controller and enables ModPHY SPD gating (PCH-LP only).
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**/
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VOID
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PmcDisableScsEmmc (
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VOID
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)
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{
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ASSERT (IsPchLp ());
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//
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// Set PWRMBASE + NST_PG_FDIS_1 to disable SCS Controller in PMC
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//
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MmioOr32 (PmcGetPwrmBase () + R_PMC_PWRM_NST_PG_FDIS_1, B_PCH_LP_PMC_PWRM_NST_PG_FDIS_1_EMMC_FDIS_PMC);
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}
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/**
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This function disables (non-static power gating) SCS SD Card controller and enables ModPHY SPD gating (PCH-LP only).
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**/
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VOID
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PmcDisableScsSdCard (
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VOID
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)
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{
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UINT32 ScsDevicePgMask;
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if (IsPchLp ()) {
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ScsDevicePgMask = B_PCH_LP_PMC_PWRM_NST_PG_FDIS_1_SDCARD_FDIS_PMC;
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} else {
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ScsDevicePgMask = B_PCH_H_PMC_PWRM_NST_PG_FDIS_1_SDCARD_FDIS_PMC;
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}
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//
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// Set PWRMBASE + NST_PG_FDIS_1 to disable SCS Controller in PMC
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//
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MmioOr32 (PmcGetPwrmBase () + R_PMC_PWRM_NST_PG_FDIS_1, ScsDevicePgMask);
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}
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/**
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This function disables (non-static power gating) SCS UFS controller and enables ModPHY SPD gating (PCH-LP only).
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@param[in] UfsNum SCS UFS Device
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**/
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VOID
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PmcDisableScsUfs (
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IN UINT32 UfsNum
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)
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{
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UINT32 PchPwrmBase;
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ASSERT ((UfsNum == 0) && IsPchLp ());
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PchPwrmBase = PmcGetPwrmBase ();
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//
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// Set PWRMBASE + NST_PG_FDIS_1 to disable SCS Controller in PMC
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//
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MmioOr32 (PchPwrmBase + R_PMC_PWRM_NST_PG_FDIS_1, B_PCH_LP_PMC_PWRM_NST_PG_FDIS_1_UFS_FDIS_PMC);
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if (PmcIsModPhySusPgSupported ()) {
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//
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// Set MSPDRTREQ:
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// PchPwrmBase + R_PWRM_MODPHY_PM_CFG5[16] = 1 to enable ASL code trigger request for ModPHY SPD gating.
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//
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MmioOr32 (PchPwrmBase + R_PMC_PWRM_MODPHY_PM_CFG5, B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_UFS2);
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}
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}
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/**
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This function checks if SCS eMMC device is supported (not disabled by fuse)
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@retval SCS device support state
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**/
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BOOLEAN
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PmcIsScsEmmcSupported (
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VOID
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)
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{
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//
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// Get fuse info from PWRMBASE + FUSE_SS_DIS_RD_2
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//
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return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_FUSE_DIS_RD_2) & B_PMC_PWRM_FUSE_DIS_RD_2_EMMC_FUSE_SS_DIS) == 0);
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}
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/**
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This function checks if SCS SD Card device is supported (not disabled by fuse)
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@retval SCS device support state
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**/
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BOOLEAN
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PmcIsScsSdCardSupported (
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VOID
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)
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{
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//
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// Get fuse info from PWRMBASE + FUSE_SS_DIS_RD_2
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//
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return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_FUSE_DIS_RD_2) & B_PMC_PWRM_FUSE_DIS_RD_2_SDX_FUSE_SS_DIS) == 0);
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}
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/**
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This function checks if SCS UFS device is supported (not disabled by fuse)
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@param[in] UfsNum SCS UFS Device
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@retval SCS device support state
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**/
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BOOLEAN
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PmcIsScsUfsSupported (
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IN UINT32 UfsNum
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)
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{
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//
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// Get fuse info from PWRMBASE + FUSE_SS_DIS_RD_2
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//
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return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_FUSE_DIS_RD_2) & B_PMC_PWRM_FUSE_DIS_RD_2_UFSX2_FUSE_SS_DIS) == 0);
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}
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