/** @file
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PCH PMC Private Library implementation for Cannon Lake PCH.
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All function in this library is available for PEI, DXE, and SMM,
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But do not support UEFI RUNTIME environment call.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Uefi/UefiBaseType.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Private/Library/PmcPrivateLib.h>
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#include <Library/SataLib.h>
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#include <Library/PchInfoLib.h>
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#include <Register/PchRegsPmc.h>
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#include "PmcPrivateLibInternal.h"
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/**
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This function disables (non-static power gating) SATA and enables ModPHY SPD gating (PCH-LP only).
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@param[in] SataCtrlIndex SATA controller index
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**/
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VOID
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PmcDisableSata (
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IN UINT32 SataCtrlIndex
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)
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{
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UINT32 PchPwrmBase;
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PchPwrmBase = PmcGetPwrmBase ();
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ASSERT (SataCtrlIndex < GetPchMaxSataControllerNum ());
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//
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// Set PWRMBASE + NST_PG_FDIS_1 [22] = 1b to disable SATA Controller in PMC
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//
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MmioOr32 (PchPwrmBase + R_PMC_PWRM_NST_PG_FDIS_1, B_PMC_PWRM_NST_PG_FDIS_1_SATA_FDIS_PMC);
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if (PmcIsModPhySusPgSupported ()) {
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//
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// MPHY SUS PG supported on PCH-LP only:
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//
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// Set MSPDRTREQ:
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// PWRMBASE + R_PWRM_MODPHY_PM_CFG5[12] = 1 to enable ASL code trigger request for ModPHY SPD gating.
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//
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MmioOr32 (PchPwrmBase + R_PMC_PWRM_MODPHY_PM_CFG5, B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_SATA);
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}
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}
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/**
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This function checks if SATA device is supported (not disabled by fuse)
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@param[in] SataCtrlIndex SATA controller index
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@retval SATA support state
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**/
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BOOLEAN
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PmcIsSataSupported (
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UINT32 SataCtrlIndex
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)
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{
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ASSERT (SataCtrlIndex < GetPchMaxSataControllerNum ());
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//
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// Get fuse info from PWRMBASE + FUSE_SS_DIS_RD_2
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//
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return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_FUSE_DIS_RD_2) & B_PMC_PWRM_FUSE_DIS_RD_2_SATA_FUSE_SS_DIS) == 0);
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}
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