/** @file
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This file contains internal PSF routines for PCH PSF lib usage
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Uefi/UefiBaseType.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PchPcrLib.h>
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#include <Library/PchInfoLib.h>
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#include <Library/SataLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Register/PchRegsPsf.h>
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#include <Register/PchRegsPsfCnl.h>
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#include <Register/PchRegsPcie.h>
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#include "PchPsfPrivateLibInternal.h"
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GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mPchLpSerialIoI2cPsfRegs[] =
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{
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R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_I2C0_REG_BASE,
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R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_I2C1_REG_BASE,
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R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_I2C2_REG_BASE,
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R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_I2C3_REG_BASE,
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R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_I2C4_REG_BASE,
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R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_I2C5_REG_BASE
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};
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GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mPchHSerialIoI2cPsfRegs[] =
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{
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R_CNL_PCH_H_PSF3_PCR_T0_SHDW_I2C0_REG_BASE,
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R_CNL_PCH_H_PSF3_PCR_T0_SHDW_I2C1_REG_BASE,
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R_CNL_PCH_H_PSF3_PCR_T0_SHDW_I2C2_REG_BASE,
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R_CNL_PCH_H_PSF3_PCR_T0_SHDW_I2C3_REG_BASE
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};
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/**
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Return PSF_PORT for SerialIO I2C device
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@param[in] I2cNum Serial IO I2C device (I2C0, I2C1, ....)
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@retval PsfPort PSF PORT structure for SerialIO I2C device
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**/
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PSF_PORT
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PsfSerialIoI2cPort (
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IN UINT32 I2cNum
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)
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{
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PSF_PORT PsfPort;
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PsfPort.PsfPid = PID_PSF3;
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if (IsPchLp ()) {
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if (I2cNum < ARRAY_SIZE(mPchLpSerialIoI2cPsfRegs)) {
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PsfPort.RegBase = mPchLpSerialIoI2cPsfRegs[I2cNum];
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return PsfPort;
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}
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} else {
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if (I2cNum < ARRAY_SIZE(mPchHSerialIoI2cPsfRegs)) {
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PsfPort.RegBase = mPchHSerialIoI2cPsfRegs[I2cNum];
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return PsfPort;
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}
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}
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ASSERT(FALSE);
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return PSF_PORT_NULL;
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}
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GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mPchLpSerialIoSpiPsfRegs[] =
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{
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R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_SPI0_REG_BASE,
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R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_SPI1_REG_BASE,
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R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_SPI2_REG_BASE
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};
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GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mPchHSerialIoSpiPsfRegs[] =
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{
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R_CNL_PCH_H_PSF3_PCR_T0_SHDW_SPI0_REG_BASE,
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R_CNL_PCH_H_PSF3_PCR_T0_SHDW_SPI1_REG_BASE,
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R_CNL_PCH_H_PSF3_PCR_T0_SHDW_SPI2_REG_BASE
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};
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/**
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Return PSF_PORT for SerialIO SPI device
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@param[in] SpiNum Serial IO SPI device (SPI0, SPI1, ....)
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@retval PsfPort PSF PORT structure for SerialIO SPI device
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**/
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PSF_PORT
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PsfSerialIoSpiPort (
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IN UINT32 SpiNum
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)
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{
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PSF_PORT PsfPort;
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PsfPort.PsfPid = PID_PSF3;
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if (IsPchLp ()) {
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if (SpiNum < ARRAY_SIZE(mPchLpSerialIoSpiPsfRegs)) {
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PsfPort.RegBase = mPchLpSerialIoSpiPsfRegs[SpiNum];
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return PsfPort;
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}
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} else {
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if (SpiNum < ARRAY_SIZE(mPchHSerialIoSpiPsfRegs)) {
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PsfPort.RegBase = mPchHSerialIoSpiPsfRegs[SpiNum];
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return PsfPort;
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}
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}
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ASSERT(FALSE);
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return PSF_PORT_NULL;
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}
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GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mPchLpSerialIoUartPsfRegs[] =
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{
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R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_UART0_REG_BASE,
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R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_UART1_REG_BASE,
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R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_UART2_REG_BASE
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};
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GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mPchHSerialIoUartPsfRegs[] =
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{
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R_CNL_PCH_H_PSF3_PCR_T0_SHDW_UART0_REG_BASE,
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R_CNL_PCH_H_PSF3_PCR_T0_SHDW_UART1_REG_BASE,
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R_CNL_PCH_H_PSF3_PCR_T0_SHDW_UART2_REG_BASE
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};
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/**
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Return PSF_PORT for SerialIO UART device
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@param[in] UartNum Serial IO UART device (UART0, UART1, ....)
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@retval PsfPort PSF PORT structure for SerialIO UART device
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**/
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PSF_PORT
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PsfSerialIoUartPort (
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IN UINT32 UartNum
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)
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{
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PSF_PORT PsfPort;
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PsfPort.PsfPid = PID_PSF3;
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if (IsPchLp ()) {
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if (UartNum < ARRAY_SIZE(mPchLpSerialIoUartPsfRegs)) {
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PsfPort.RegBase = mPchLpSerialIoUartPsfRegs[UartNum];
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return PsfPort;
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}
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} else {
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if (UartNum < ARRAY_SIZE(mPchHSerialIoUartPsfRegs)) {
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PsfPort.RegBase = mPchHSerialIoUartPsfRegs[UartNum];
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return PsfPort;
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}
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}
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ASSERT(FALSE);
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return PSF_PORT_NULL;
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}
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/**
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Get EOI register data for given PSF ID
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@param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...)
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@param[out] EoiTargetBase EOI Target register
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@param[out] EoiControlBase EOI Control register
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@retval MaxTargets Number of supported targets
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**/
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UINT8
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PsfEoiRegData (
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UINT32 PsfId,
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UINT16 *EoiTargetBase,
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UINT16 *EoiControlBase
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)
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{
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UINT8 MaxTargets;
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MaxTargets = 0;
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*EoiTargetBase = 0;
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*EoiControlBase = 0;
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switch (PsfId) {
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case 1:
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if (IsPchLp ()) {
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*EoiTargetBase = R_CNL_PCH_LP_PSF1_PCR_PSF_MC_AGENT_MCAST0_TGT0_EOI;
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*EoiControlBase = R_CNL_PCH_LP_PSF1_PCR_PSF_MC_CONTROL_MCAST0_EOI;
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MaxTargets = 17;
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} else {
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*EoiTargetBase = R_CNL_PCH_H_PSF1_PCR_PSF_MC_AGENT_MCAST0_TGT0_EOI;
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*EoiControlBase = R_CNL_PCH_H_PSF1_PCR_PSF_MC_CONTROL_MCAST0_EOI;
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MaxTargets = 7;
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}
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break;
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case 3:
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*EoiTargetBase = R_CNL_PCH_PSF3_PCR_PSF_MC_AGENT_MCAST0_TGT0_EOI;
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*EoiControlBase = R_CNL_PCH_PSF3_PCR_PSF_MC_CONTROL_MCAST0_EOI;
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MaxTargets = 1;
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break;
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case 6:
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if (IsPchH ()) {
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*EoiTargetBase = R_CNL_PCH_H_PSF6_PCR_PSF_MC_AGENT_MCAST0_TGT0_EOI;
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*EoiControlBase = R_CNL_PCH_H_PSF6_PCR_PSF_MC_CONTROL_MCAST0_EOI;
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MaxTargets = 8;
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}
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break;
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case 7:
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if (IsPchH ()) {
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*EoiTargetBase = R_CNL_PCH_H_PSF7_PCR_PSF_MC_AGENT_MCAST0_TGT0_EOI;
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*EoiControlBase = R_CNL_PCH_H_PSF7_PCR_PSF_MC_CONTROL_MCAST0_EOI;
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MaxTargets = 8;
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}
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break;
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case 8:
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if (IsPchH ()) {
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*EoiTargetBase = R_CNL_PCH_H_PSF8_PCR_PSF_MC_AGENT_MCAST0_TGT0_EOI;
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*EoiControlBase = R_CNL_PCH_H_PSF8_PCR_PSF_MC_CONTROL_MCAST0_EOI;
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MaxTargets = 8;
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}
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break;
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}
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return MaxTargets;
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}
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GLOBAL_REMOVE_IF_UNREFERENCED PSF_PORT_DEST_ID PchLpRpDestId[] =
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{
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{0x18000}, {0x18001}, {0x18002}, {0x18003}, // SPA: PSF1, PortID = 0
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{0x18200}, {0x18201}, {0x18202}, {0x18203}, // SPB: PSF1, PortID = 2
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{0x18400}, {0x18401}, {0x18402}, {0x18403}, // SPC: PSF1, PortID = 4
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{0x18600}, {0x18601}, {0x18602}, {0x18603} // SPD: PSF1, PortID = 6
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};
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GLOBAL_REMOVE_IF_UNREFERENCED PSF_PORT_DEST_ID PchHRpDestId[] =
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{
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{0x68000}, {0x68001}, {0x68002}, {0x68003}, // SPA: PSF6, PortID = 0
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{0x88000}, {0x88001}, {0x88002}, {0x88003}, // SPB: PSF8, PortID = 0
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{0x68100}, {0x68101}, {0x68102}, {0x68103}, // SPC: PSF6, PortID = 1
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{0x78000}, {0x78001}, {0x78002}, {0x78003}, // SPD: PSF7, PortID = 0
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{0x78100}, {0x78101}, {0x78102}, {0x78103}, // SPE: PSF7, PortID = 1
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{0x88100}, {0x88101}, {0x88102}, {0x88103} // SPF: PSF8, PortID = 1
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};
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/**
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PCIe PSF port destination ID (psf_id:port_group_id:port_id:channel_id)
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@param[in] RpIndex PCIe Root Port Index (0 based)
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@retval Destination ID
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**/
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PSF_PORT_DEST_ID
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PsfPcieDestinationId (
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IN UINT32 RpIndex
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)
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{
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if (IsPchLp ()) {
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if (RpIndex < ARRAY_SIZE(PchLpRpDestId)) {
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return PchLpRpDestId[RpIndex];
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}
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} else {
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if (RpIndex < ARRAY_SIZE(PchHRpDestId)) {
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return PchHRpDestId[RpIndex];
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}
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}
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ASSERT (FALSE);
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return (PSF_PORT_DEST_ID){0};
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}
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/**
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Return PSF_PORT for PMC device
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@retval PsfPort PSF PORT structure for PMC device
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**/
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PSF_PORT
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PsfPmcPort (
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VOID
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)
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{
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PSF_PORT PsfPort;
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PsfPort.PsfPid = PID_PSF3;
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if (IsPchLp ()) {
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PsfPort.RegBase = R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_PMC_REG_BASE;
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} else {
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PsfPort.RegBase = R_CNL_PCH_H_PSF3_PCR_T0_SHDW_PMC_REG_BASE;
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}
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return PsfPort;
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}
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GLOBAL_REMOVE_IF_UNREFERENCED PSF_SEGMENT mPchLpPsfTable[] =
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{
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{1, PID_PSF1},
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{2, PID_PSF2},
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{3, PID_PSF3},
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{4, PID_PSF4},
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{5, PID_CSME_PSF}
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};
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GLOBAL_REMOVE_IF_UNREFERENCED PSF_SEGMENT mPchHPsfTable[] =
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{
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{1, PID_PSF1},
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{2, PID_PSF2},
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{3, PID_PSF3},
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{4, PID_PSF4},
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{5, PID_CSME_PSF},
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{6, PID_PSF6},
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{7, PID_PSF7},
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{8, PID_PSF8}
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};
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/**
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Get list of supported PSF segments.
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@param[out] PsfTable Array of supported PSF segments
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@param[out] PsfTableLength Length of PsfTable
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**/
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VOID
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PsfSegments (
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OUT PSF_SEGMENT **PsfTable,
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OUT UINT32 *PsfTableLength
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)
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{
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if (IsPchLp ()) {
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*PsfTable = mPchLpPsfTable;
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*PsfTableLength = ARRAY_SIZE(mPchLpPsfTable);
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} else {
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*PsfTable = mPchHPsfTable;
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*PsfTableLength = ARRAY_SIZE(mPchHPsfTable);
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}
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}
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