/** @file
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System reset library services.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/PciSegmentLib.h>
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#include <Library/PchResetLib.h>
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#include <Library/ResetSystemLib.h>
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#include <Library/PmcLib.h>
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#include <Private/Library/PmcPrivateLib.h>
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#include <Ppi/PchReset.h>
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#include <Register/PchRegsLpc.h>
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#include <Register/PchRegsPmc.h>
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/**
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Dump reset message for debug build readability
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**/
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VOID
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DumpResetMessage (
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VOID
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)
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{
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DEBUG_CODE_BEGIN ();
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UINTN Index;
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//
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// ******************************
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// ** SYSTEM REBOOT !!! **
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// ******************************
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//
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for (Index = 0; Index < 30; Index++) {
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DEBUG ((DEBUG_INFO, "*"));
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}
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DEBUG ((DEBUG_INFO, "\n** SYSTEM REBOOT !!! **\n"));
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for (Index = 0; Index < 30; Index++) {
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DEBUG ((DEBUG_INFO, "*"));
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}
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DEBUG ((DEBUG_INFO, "\n"));
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DEBUG_CODE_END ();
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}
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/**
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Execute call back function for Pch Reset.
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@param[in] ResetType Reset Types which includes GlobalReset.
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@param[in] ResetTypeGuid Pointer to an EFI_GUID, which is the Reset Type Guid.
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**/
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VOID
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PchResetCallback (
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IN EFI_RESET_TYPE ResetType,
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IN EFI_GUID *ResetTypeGuid
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)
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{
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EFI_STATUS Status;
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UINTN Instance;
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PCH_RESET_CALLBACK_PPI *PchResetCallbackPpi;
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Instance = 0;
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do {
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Status = PeiServicesLocatePpi (
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&gPchResetCallbackPpiGuid,
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Instance,
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NULL,
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(VOID **) &PchResetCallbackPpi
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);
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switch (Status) {
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case EFI_SUCCESS:
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PchResetCallbackPpi->ResetCallback (ResetType, ResetTypeGuid);
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break;
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case EFI_NOT_FOUND:
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break;
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default:
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ASSERT_EFI_ERROR (Status);
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break;
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}
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++Instance;
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} while (Status == EFI_SUCCESS);
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}
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/**
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Calling this function causes a system-wide reset. This sets
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all circuitry within the system to its initial state. This type of reset
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is asynchronous to system operation and operates without regard to
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cycle boundaries.
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System reset should not return, if it returns, it means the system does
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not support cold reset.
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**/
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VOID
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EFIAPI
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ResetCold (
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VOID
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)
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{
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//
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// Loop through callback functions of PchResetCallback PPI
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//
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PchResetCallback (EfiResetCold, NULL);
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DumpResetMessage ();
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IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_FULLRESET);
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}
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/**
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Calling this function causes a system-wide initialization. The processors
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are set to their initial state, and pending cycles are not corrupted.
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System reset should not return, if it returns, it means the system does
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not support warm reset.
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**/
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VOID
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EFIAPI
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ResetWarm (
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VOID
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)
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{
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//
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// Loop through callback functions of PchResetCallback PPI
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//
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PchResetCallback (EfiResetWarm, NULL);
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DumpResetMessage ();
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IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_HARDRESET);
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}
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/**
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Calling this function causes the system to enter a power state equivalent
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to the ACPI G2/S5 or G3 states.
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System shutdown should not return, if it returns, it means the system does
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not support shut down reset.
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**/
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VOID
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EFIAPI
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ResetShutdown (
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VOID
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)
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{
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UINT16 ABase;
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UINT32 Data32;
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//
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// Loop through callback functions of PchResetCallback PPI
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//
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PchResetCallback (EfiResetShutdown, NULL);
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ABase = PmcGetAcpiBase ();
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///
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/// Firstly, GPE0_EN should be disabled to avoid any GPI waking up the system from S5
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///
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IoWrite32 ((UINTN) (ABase + R_ACPI_IO_GPE0_EN_127_96), 0);
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///
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/// Secondly, PwrSts register must be cleared
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///
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/// Write a "1" to bit[8] of power button status register at
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/// (PM_BASE + PM1_STS_OFFSET) to clear this bit
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///
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IoWrite16 ((UINTN) (ABase + R_ACPI_IO_PM1_STS), B_ACPI_IO_PM1_STS_PWRBTN);
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///
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/// Finally, transform system into S5 sleep state
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///
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Data32 = IoRead32 ((UINTN) (ABase + R_ACPI_IO_PM1_CNT));
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Data32 = (UINT32) ((Data32 &~(B_ACPI_IO_PM1_CNT_SLP_TYP + B_ACPI_IO_PM1_CNT_SLP_EN)) | V_ACPI_IO_PM1_CNT_S5);
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IoWrite32 ((UINTN) (ABase + R_ACPI_IO_PM1_CNT), Data32);
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Data32 = Data32 | B_ACPI_IO_PM1_CNT_SLP_EN;
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DumpResetMessage ();
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IoWrite32 ((UINTN) (ABase + R_ACPI_IO_PM1_CNT), Data32);
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return;
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}
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/**
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Internal function to execute the required HECI command for GlobalReset,
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if failed will use PCH Reest.
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**/
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STATIC
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VOID
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PchGlobalReset (
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VOID
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)
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{
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//
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// Loop through callback functions of PchResetCallback PPI
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//
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PchResetCallback (EfiResetPlatformSpecific, &gPchGlobalResetGuid);
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//
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// PCH BIOS Spec Section 4.6 GPIO Reset Requirement
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//
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PmcEnableCf9GlobalReset ();
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DumpResetMessage ();
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IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_FULLRESET);
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}
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/**
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Calling this function causes the system to enter a power state for platform specific.
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@param[in] DataSize The size of ResetData in bytes.
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@param[in] ResetData Optional element used to introduce a platform specific reset.
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The exact type of the reset is defined by the EFI_GUID that follows
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the Null-terminated Unicode string.
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**/
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VOID
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EFIAPI
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ResetPlatformSpecific (
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IN UINTN DataSize,
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IN VOID *ResetData OPTIONAL
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)
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{
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EFI_GUID *GuidPtr;
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if (ResetData == NULL) {
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DEBUG ((DEBUG_ERROR, "[PeiResetSystemLib] ResetData is not available.\n"));
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return;
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}
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GuidPtr = (EFI_GUID *) ((UINT8 *) ResetData + DataSize - sizeof (EFI_GUID));
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if (CompareGuid (GuidPtr, &gPchGlobalResetGuid)) {
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PchGlobalReset();
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} else {
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return;
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}
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}
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/**
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Calling this function causes the system to enter a power state for capsule update.
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Reset update should not return, if it returns, it means the system does
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not support capsule update.
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**/
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VOID
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EFIAPI
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EnterS3WithImmediateWake (
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VOID
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)
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{
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ASSERT (FALSE);
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}
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