/** @file
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PCH PMC Library.
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All function in this library is available for PEI, DXE, and SMM,
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But do not support UEFI RUNTIME environment call.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Uefi/UefiBaseType.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/PciSegmentLib.h>
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#include <Library/PchCycleDecodingLib.h>
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#include <Library/PmcLib.h>
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#include <Library/PchPcrLib.h>
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#include <Library/PchInfoLib.h>
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#include <Private/Library/PmcPrivateLib.h>
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#include <PchReservedResources.h>
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#include <Register/PchRegsPmc.h>
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/**
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Get PCH ACPI base address.
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@retval Address Address of PWRM base address.
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**/
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UINT16
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PmcGetAcpiBase (
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VOID
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)
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{
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return PcdGet16 (PcdAcpiBaseAddress);
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}
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/**
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Get PCH PWRM base address.
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@retval Address Address of PWRM base address.
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**/
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UINT32
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PmcGetPwrmBase (
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VOID
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)
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{
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return PCH_PWRM_BASE_ADDRESS;
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}
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/**
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This function enables Power Button SMI
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**/
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VOID
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PmcEnablePowerButtonSmi (
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VOID
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)
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{
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IoOr16 (PmcGetAcpiBase () + R_ACPI_IO_PM1_EN, B_ACPI_IO_PM1_EN_PWRBTN);
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}
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/**
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This function disables Power Button SMI
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**/
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VOID
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PmcDisablePowerButtonSmi (
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VOID
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)
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{
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IoAnd16 (PmcGetAcpiBase () + R_ACPI_IO_PM1_EN, (UINT16)~B_ACPI_IO_PM1_EN_PWRBTN);
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}
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/**
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This function reads PM Timer Count driven by 3.579545 MHz clock
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@retval PM Timer Count
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**/
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UINT32
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PmcGetTimerCount (
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VOID
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)
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{
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return IoRead32 (PmcGetAcpiBase () + R_ACPI_IO_PM1_TMR) & B_ACPI_IO_PM1_TMR_VAL;
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}
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/**
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Get Sleep Type that platform has waken from
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@retval SleepType Sleep Type
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**/
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PMC_SLEEP_STATE
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PmcGetSleepTypeAfterWake (
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VOID
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)
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{
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UINT16 AcpiBase;
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UINT32 PmconA;
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AcpiBase = PmcGetAcpiBase ();
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PmconA = MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A);
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DEBUG ((DEBUG_INFO, "PWRM_PMCON_A = 0x%x\n", PmconA));
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//
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// If Global Reset Status, Power Failure. Host Reset Status bits are set, return S5 State
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//
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if ((PmconA & (B_PMC_PWRM_GEN_PMCON_A_GBL_RST_STS | B_PMC_PWRM_GEN_PMCON_A_PWR_FLR | B_PMC_PWRM_GEN_PMCON_A_HOST_RST_STS)) != 0) {
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return PmcNotASleepState;
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}
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if (IoRead16 (AcpiBase + R_ACPI_IO_PM1_STS) & B_ACPI_IO_PM1_STS_WAK) {
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switch (IoRead16 (AcpiBase + R_ACPI_IO_PM1_CNT) & B_ACPI_IO_PM1_CNT_SLP_TYP) {
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case V_ACPI_IO_PM1_CNT_S0:
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return PmcInS0State;
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case V_ACPI_IO_PM1_CNT_S1:
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return PmcS1SleepState;
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case V_ACPI_IO_PM1_CNT_S3:
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return PmcS3SleepState;
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case V_ACPI_IO_PM1_CNT_S4:
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return PmcS4SleepState;
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case V_ACPI_IO_PM1_CNT_S5:
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return PmcS5SleepState;
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default:
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ASSERT (FALSE);
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return PmcUndefinedState;
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}
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} else {
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return PmcNotASleepState;
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}
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}
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/**
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Clear PMC Wake Status
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**/
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VOID
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PmcClearWakeStatus (
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VOID
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)
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{
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IoWrite16 (PmcGetAcpiBase () + R_ACPI_IO_PM1_STS, B_ACPI_IO_PM1_STS_WAK);
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}
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/**
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Check if platform boots after shutdown caused by power button override event
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@retval TRUE Power Button Override occurred in last system boot
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@retval FALSE Power Button Override didn't occur
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**/
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BOOLEAN
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PmcIsPowerButtonOverrideDetected (
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VOID
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)
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{
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return ((IoRead16 (PmcGetAcpiBase () + R_ACPI_IO_PM1_STS) & B_ACPI_IO_PM1_STS_PRBTNOR) != 0);
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}
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/**
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This function checks if RTC Power Failure occurred by
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reading RTC_PWR_FLR bit
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@retval RTC Power Failure state: TRUE - Battery is always present.
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FALSE - CMOS is cleared.
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**/
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BOOLEAN
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PmcIsRtcBatteryGood (
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VOID
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)
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{
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return ((MmioRead8 (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_B) & B_PMC_PWRM_GEN_PMCON_B_RTC_PWR_STS) == 0);
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}
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/**
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This function checks if Power Failure occurred by
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reading PWR_FLR bit
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@retval Power Failure state
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**/
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BOOLEAN
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PmcIsPowerFailureDetected (
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VOID
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)
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{
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return ((MmioRead16 (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A) & B_PMC_PWRM_GEN_PMCON_A_PWR_FLR) != 0);
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}
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/**
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This function checks if RTC Power Failure occurred by
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reading SUS_PWR_FLR bit
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@retval SUS Power Failure state
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**/
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BOOLEAN
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PmcIsSusPowerFailureDetected (
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VOID
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)
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{
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return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_B) & B_PMC_PWRM_GEN_PMCON_A_SUS_PWR_FLR) != 0);
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}
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/**
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This function clears Power Failure status (PWR_FLR)
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**/
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VOID
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PmcClearPowerFailureStatus (
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VOID
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)
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{
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//
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// Write 1 to clear PWR_FLR
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// Avoid clearing other W1C bits
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//
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MmioAndThenOr8 (
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PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A + 1,
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(UINT8) ~(B_PMC_PWRM_GEN_PMCON_A_HOST_RST_STS >> 8),
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B_PMC_PWRM_GEN_PMCON_A_PWR_FLR >> 8
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);
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}
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/**
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This function clears Global Reset status (GBL_RST_STS)
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**/
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VOID
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PmcClearGlobalResetStatus (
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VOID
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)
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{
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//
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// Write 1 to clear GBL_RST_STS
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// Avoid clearing other W1C bits
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//
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MmioAndThenOr8 (
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PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A + 3,
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(UINT8) ~0,
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B_PMC_PWRM_GEN_PMCON_A_GBL_RST_STS >> 24
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);
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}
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/**
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This function clears Host Reset status (HOST_RST_STS)
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**/
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VOID
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PmcClearHostResetStatus (
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VOID
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)
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{
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//
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// Write 1 to clear HOST_RST_STS
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// Avoid clearing other W1C bits
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//
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MmioAndThenOr8 (
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PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A + 1,
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(UINT8) ~(B_PMC_PWRM_GEN_PMCON_A_PWR_FLR >> 8),
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B_PMC_PWRM_GEN_PMCON_A_HOST_RST_STS >> 8
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);
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}
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/**
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This function clears SUS Power Failure status (SUS_PWR_FLR)
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**/
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VOID
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PmcClearSusPowerFailureStatus (
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VOID
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)
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{
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//
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// BIOS clears this bit by writing a '1' to it.
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// Take care of other fields, so we don't clear them accidentally.
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//
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MmioAndThenOr8 (
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PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A + 2,
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(UINT8) ~(B_PMC_PWRM_GEN_PMCON_A_MS4V >> 16),
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B_PMC_PWRM_GEN_PMCON_A_SUS_PWR_FLR >> 16
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);
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}
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/**
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This function sets state to which platform will get after power is reapplied
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@param[in] PowerStateAfterG3 0: S0 state (boot)
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1: S5/S4 State
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**/
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VOID
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PmcSetPlatformStateAfterPowerFailure (
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IN UINT8 PowerStateAfterG3
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)
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{
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UINT32 PchPwrmBase;
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PchPwrmBase = PmcGetPwrmBase ();
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if (PowerStateAfterG3) {
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MmioOr8 (PchPwrmBase + R_PMC_PWRM_GEN_PMCON_A, B_PMC_PWRM_GEN_PMCON_A_AFTERG3_EN);
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} else {
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MmioAnd8 (PchPwrmBase + R_PMC_PWRM_GEN_PMCON_A, (UINT8)~B_PMC_PWRM_GEN_PMCON_A_AFTERG3_EN);
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}
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}
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/**
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This function checks if SMI Lock is set
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@retval SMI Lock state
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**/
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BOOLEAN
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PmcIsSmiLockSet (
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VOID
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)
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{
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return ((MmioRead8 ((UINTN) (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_B)) & B_PMC_PWRM_GEN_PMCON_B_SMI_LOCK) != 0);
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}
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/**
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Check global SMI enable is set
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@retval TRUE Global SMI enable is set
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FALSE Global SMI enable is not set
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**/
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BOOLEAN
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PmcIsGblSmiEn (
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VOID
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)
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{
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return !!(IoRead32 (PmcGetAcpiBase () + R_ACPI_IO_SMI_EN) & B_ACPI_IO_SMI_EN_GBL_SMI);
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}
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